[llvm] [TableGen][GISel] Create untyped registers during instruction selection (PR #121270)

[Sergei Barannikov via llvm-commits]

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@@ -1485,15 +1485,28 @@ bool GIMatchTableExecutor::executeMatchTable(
       propagateFlags();
       return true;
     }
-    case GIR_MakeTempReg: {
+    case GIR_MakeGenericTempReg: {
       uint64_t TempRegID = readULEB();
       int TypeID = readS8();
 
       State.TempRegisters[TempRegID] =
           MRI.createGenericVirtualRegister(getTypeFromIdx(TypeID));
-      DEBUG_WITH_TYPE(TgtExecutor::getName(),
-                      dbgs() << CurrentIdx << ": TempRegs[" << TempRegID
-                             << "] = GIR_MakeTempReg(" << TypeID << ")\n");
+      DEBUG_WITH_TYPE(TgtExecutor::getName(), {
+        dbgs() << CurrentIdx << ": TempRegs[" << TempRegID
+               << "] = GIR_MakeGenericTempReg(" << TypeID << ")\n";
+      });
+      break;
+    }
+    case GIR_MakeVirtualTempReg: {
+      uint64_t TempRegID = readULEB();
+
+      Register Reg = MRI.createIncompleteVirtualRegister();
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s-barannikov wrote:

I'm confused. 

> An additional copy is only needed if getCommonSubClass for the producer and consumer can't find anything. I guess we could handle that in the selector implementation

If we delay emitting this copy, then the register's class would be invalid for the consumer and we shouldn't make decisions based on invalid register class either.

> this doesn't work for instructions that do not have concrete register class constraints

This is new to me. How can instruction's register operand not have a concrete register class?


https://github.com/llvm/llvm-project/pull/121270