[llvm] [RISCV][VLOPT] Add strided, unit strided, and indexed loads to isSupported (PR #121705)

[Michael Maitland via llvm-commits]

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@@ -732,6 +747,30 @@ static bool isSupportedInstr(const MachineInstr &MI) {
     return false;
 
   switch (RVV->BaseInstr) {
+  // Vector Unit-Stride Instructions
+  // Vector Strided Instructions
+  case RISCV::VLE8_V:
+  case RISCV::VLM_V:
+  case RISCV::VLSE8_V:
+  case RISCV::VLE8FF_V:
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michaelmaitland wrote:

If it had its AVL reduced, which caused a fault which would have happened to no longer occur, would this produce a different result?

https://github.com/llvm/llvm-project/pull/121705