[llvm] [RISCV][VLOPT] Add strided, unit strided, and indexed loads to isSupported (PR #121705)

[Luke Lau via llvm-commits]

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@@ -732,6 +747,30 @@ static bool isSupportedInstr(const MachineInstr &MI) {
     return false;
 
   switch (RVV->BaseInstr) {
+  // Vector Unit-Stride Instructions
+  // Vector Strided Instructions
+  case RISCV::VLE8_V:
+  case RISCV::VLM_V:
+  case RISCV::VLSE8_V:
+  case RISCV::VLE8FF_V:
----------------
lukel97 wrote:

It will affect the resulting VL though. I'm thinking if someone wrote something like:

```llvm
  %a = call { <vscale x 1 x i64>, i64 } @llvm.riscv.vleff.nxv1i64(<vscale x 1 x i64> undef, ptr %0, i64 %avl)
  %vl.ff = extractvalue { <vscale x 1 x i64>, i64 } %a, 1
```

%vl.ff might change if the vleff had its AVL reduced.

https://github.com/llvm/llvm-project/pull/121705