[llvm] [AMDGPU][MC] Allow null where 128b or larger dst reg is expected (PR #115200)

[Jun Wang via llvm-commits]

================
@@ -881,10 +885,12 @@ def SReg_1 : SIRegisterClass<"AMDGPU", [i1], 32,
   let HasSGPR = 1;
 }
 
+
 multiclass SRegClass<int numRegs,
                      list<ValueType> regTypes,
                      SIRegisterTuples regList,
                      SIRegisterTuples ttmpList = regList,
+                     bit hasNull = 0,
                      int copyCost = !sra(!add(numRegs, 1), 1)> {
----------------
jwanggit86 wrote:

Agreed, but I think I'll leave it as is unless you think it should be fixed.

https://github.com/llvm/llvm-project/pull/115200