[llvm] [AMDGPU][MC] Allow null where 128b or larger dst reg is expected (PR #115200)

[Jay Foad via llvm-commits]

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@@ -910,22 +916,31 @@ multiclass SRegClass<int numRegs,
       let isAllocatable = 0;
       let BaseClassOrder = !mul(numRegs, 32);
     }
+
+    if hasNull then {
+      def SReg_ # suffix :
+        SIRegisterClass<"AMDGPU", regTypes, 32,
+                      !dag(add, [!cast<RegisterClass>("SReg_" # suffix # "_XNULL"), !cast<Register>("SGPR_NULL" # suffix)], ["", ""])> {
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jayfoad wrote:

OK but I don't see why you need to use `!dag`. You can write it literally as `(add !cast<RegisterClass>("SReg_" # suffix # "_XNULL"), !cast<Register>("SGPR_NULL" # suffix))`.

https://github.com/llvm/llvm-project/pull/115200