[llvm] [AMDGPU][MC] Allow null where 128b or larger dst reg is expected (PR #115200)

[Jun Wang via llvm-commits]

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@@ -809,6 +809,10 @@ def SReg_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16,
   let BaseClassOrder = 32;
 }
 
+def SGPR_NULL128 : SIReg<"null">;
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jwanggit86 wrote:

I was actually not very sure if this def is correct. SGPR_NULL64 is defined with 2 sub-regs. I wasn't sure if SGPR_128NULL should be defined similarly, and if so, what the sub-regs should be. On the other hand, changing SGPR_NULL64 to `def SGPR_NULL64: SIReg<"null">` would fail a lot of tests, possibly because SReg_64 is used when it should really be SReg_64_XNULL. Any suggestions are appreciated.

https://github.com/llvm/llvm-project/pull/115200