[llvm] 133352f - [test] Remove redundant -march= when target triple is specified in IR
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 15 12:42:23 PST 2024
Author: Fangrui Song
Date: 2024-12-15T12:42:17-08:00
New Revision: 133352feb30605ec51b15f77826ed3a2fbf8db56
URL: https://github.com/llvm/llvm-project/commit/133352feb30605ec51b15f77826ed3a2fbf8db56
DIFF: https://github.com/llvm/llvm-project/commit/133352feb30605ec51b15f77826ed3a2fbf8db56.diff
LOG: [test] Remove redundant -march= when target triple is specified in IR
Added:
Modified:
llvm/test/CodeGen/AArch64/stack-tagging-ex-2.ll
llvm/test/CodeGen/Hexagon/autohvx/float-cost.ll
llvm/test/CodeGen/Hexagon/autohvx/interleave.ll
llvm/test/CodeGen/Hexagon/autohvx/maximize-bandwidth.ll
llvm/test/CodeGen/Hexagon/bug15515-shuffle.ll
llvm/test/CodeGen/Hexagon/const-pool-tf.ll
llvm/test/CodeGen/Hexagon/glob-align-volatile.ll
llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll
llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-long-loop.ll
llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll
llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-shiftconv-fail.ll
llvm/test/CodeGen/Hexagon/vcombine_zero_diff_ptrs.ll
llvm/test/CodeGen/Lanai/delay_filler.ll
llvm/test/CodeGen/Lanai/lowering-128.ll
llvm/test/CodeGen/NVPTX/surf-read.ll
llvm/test/CodeGen/NVPTX/surf-write.ll
llvm/test/CodeGen/NVPTX/tex-read.ll
llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll
llvm/test/CodeGen/Thumb2/bug-subw.ll
llvm/test/DebugInfo/NVPTX/debug-ptx-symbols.ll
llvm/test/DebugInfo/X86/instr-ref-flag.ll
llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll
llvm/test/DebugInfo/X86/single-dbg_value.ll
llvm/test/Transforms/LoadStoreVectorizer/NVPTX/propagate-invariance-metadata.ll
llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll
llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/speculative-slsr.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/stack-tagging-ex-2.ll b/llvm/test/CodeGen/AArch64/stack-tagging-ex-2.ll
index 99e593b878a766..e5725bcf66fdf3 100644
--- a/llvm/test/CodeGen/AArch64/stack-tagging-ex-2.ll
+++ b/llvm/test/CodeGen/AArch64/stack-tagging-ex-2.ll
@@ -1,4 +1,4 @@
-; clang -target aarch64-eabi -O2 -march=armv8.5-a+memtag -fsanitize=memtag -S -emit-llvm test.cc
+; clang -target aarch64-eabi -O2 -fsanitize=memtag -S -emit-llvm test.cc
; void bar() {
; throw 42;
; }
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/float-cost.ll b/llvm/test/CodeGen/Hexagon/autohvx/float-cost.ll
index 089bc9967d08f7..614184ed9b5346 100644
--- a/llvm/test/CodeGen/Hexagon/autohvx/float-cost.ll
+++ b/llvm/test/CodeGen/Hexagon/autohvx/float-cost.ll
@@ -1,4 +1,4 @@
-; RUN: opt -march=hexagon -passes=loop-vectorize -hexagon-autohvx -debug-only=loop-vectorize -S < %s 2>&1 | FileCheck %s
+; RUN: opt -passes=loop-vectorize -hexagon-autohvx -debug-only=loop-vectorize -S < %s 2>&1 | FileCheck %s
; REQUIRES: asserts
; Check that the cost model makes vectorization non-profitable.
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/interleave.ll b/llvm/test/CodeGen/Hexagon/autohvx/interleave.ll
index a4b24a1a61100f..0a3ee5e12a2c30 100644
--- a/llvm/test/CodeGen/Hexagon/autohvx/interleave.ll
+++ b/llvm/test/CodeGen/Hexagon/autohvx/interleave.ll
@@ -1,4 +1,4 @@
-; RUN: opt -march=hexagon -hexagon-autohvx -passes=loop-vectorize -S < %s | FileCheck %s
+; RUN: opt -hexagon-autohvx -passes=loop-vectorize -S < %s | FileCheck %s
; Check that the loop has been interleaved.
; CHECK: store <64 x i32> %interleaved.vec
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/maximize-bandwidth.ll b/llvm/test/CodeGen/Hexagon/autohvx/maximize-bandwidth.ll
index e2a9f0937c84aa..4e882f2c6a04fb 100644
--- a/llvm/test/CodeGen/Hexagon/autohvx/maximize-bandwidth.ll
+++ b/llvm/test/CodeGen/Hexagon/autohvx/maximize-bandwidth.ll
@@ -1,4 +1,4 @@
-; RUN: opt -march=hexagon -hexagon-autohvx -passes=loop-vectorize -S < %s | FileCheck %s
+; RUN: opt -hexagon-autohvx -passes=loop-vectorize -S < %s | FileCheck %s
; Check that the loop is vectorized with VF=32.
; CHECK: wide.load{{.*}} = load <32 x i32>
; CHECK: wide.load{{.*}} = load <32 x i16>
diff --git a/llvm/test/CodeGen/Hexagon/bug15515-shuffle.ll b/llvm/test/CodeGen/Hexagon/bug15515-shuffle.ll
index 5b3894a5b6afa7..2dc69dbb200ef6 100644
--- a/llvm/test/CodeGen/Hexagon/bug15515-shuffle.ll
+++ b/llvm/test/CodeGen/Hexagon/bug15515-shuffle.ll
@@ -1,4 +1,4 @@
-; RUN: opt -march=hexagon -O2 -S < %s
+; RUN: opt -O2 -S < %s
; REQUIRES: asserts
;
; -fvectorize-loops infinite compile/memory
diff --git a/llvm/test/CodeGen/Hexagon/const-pool-tf.ll b/llvm/test/CodeGen/Hexagon/const-pool-tf.ll
index ab804cacf15d19..a889d4dae63781 100644
--- a/llvm/test/CodeGen/Hexagon/const-pool-tf.ll
+++ b/llvm/test/CodeGen/Hexagon/const-pool-tf.ll
@@ -1,4 +1,4 @@
-; RUN: opt -relocation-model pic -mtriple=hexagon -mcpu=hexagonv60 -O2 -S < %s | llc -march=hexagon -mcpu=hexagonv60 -relocation-model pic
+; RUN: opt -relocation-model pic -mtriple=hexagon -mcpu=hexagonv60 -O2 -S < %s | llc -mcpu=hexagonv60 -relocation-model pic
; CHECK: jumpr
diff --git a/llvm/test/CodeGen/Hexagon/glob-align-volatile.ll b/llvm/test/CodeGen/Hexagon/glob-align-volatile.ll
index 9d4cbd9bc7c80d..05ec0ae4c29cf1 100644
--- a/llvm/test/CodeGen/Hexagon/glob-align-volatile.ll
+++ b/llvm/test/CodeGen/Hexagon/glob-align-volatile.ll
@@ -1,4 +1,4 @@
-; RUN: opt -Os -march=hexagon -S < %s | FileCheck %s
+; RUN: opt -Os -S < %s | FileCheck %s
; Don't reset the alignment on the struct to 1.
; CHECK: align 4
diff --git a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll
index 74c02d63d54d32..b5639449d11312 100644
--- a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll
+++ b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll
@@ -1,5 +1,5 @@
-; RUN: opt -march=hexagon -hexagon-loop-idiom -S < %s | FileCheck %s
-; RUN: opt -march=hexagon -p hexagon-loop-idiom -S < %s | FileCheck %s
+; RUN: opt -hexagon-loop-idiom -S < %s | FileCheck %s
+; RUN: opt -p hexagon-loop-idiom -S < %s | FileCheck %s
; CHECK-LABEL: define void @fred
; Check that this test does not crash.
diff --git a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-long-loop.ll b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-long-loop.ll
index 94b0c96c3d5178..07536c7f4a508b 100644
--- a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-long-loop.ll
+++ b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-long-loop.ll
@@ -1,5 +1,5 @@
-; RUN: opt -march=hexagon -hexagon-loop-idiom -S < %s | FileCheck %s
-; RUN: opt -march=hexagon -p hexagon-loop-idiom -S < %s | FileCheck %s
+; RUN: opt -hexagon-loop-idiom -S < %s | FileCheck %s
+; RUN: opt -p hexagon-loop-idiom -S < %s | FileCheck %s
;
; The number of nested selects caused the simplification loop to take
; more than the maximum number of iterations. This caused the compiler
diff --git a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll
index 08e5f3ab1f1f50..836a0e110b9e06 100644
--- a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll
+++ b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll
@@ -2,8 +2,8 @@
; the Hexagon loop idiom recognition runs. This is to check that we still
; get this opportunity regardless of what happens before.
-; RUN: opt -O2 -march=hexagon -S < %s | FileCheck %s
-; RUN: opt -passes='default<O2>' -march=hexagon -S < %s | FileCheck %s
+; RUN: opt -O2 -S < %s | FileCheck %s
+; RUN: opt -passes='default<O2>' -S < %s | FileCheck %s
target triple = "hexagon"
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
diff --git a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-shiftconv-fail.ll b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-shiftconv-fail.ll
index a00b1d5876ba89..a0fcba15c35da3 100644
--- a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-shiftconv-fail.ll
+++ b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-shiftconv-fail.ll
@@ -1,5 +1,5 @@
-; RUN: opt -march=hexagon -hexagon-loop-idiom -S < %s | FileCheck %s
-; RUN: opt -march=hexagon -p hexagon-loop-idiom -S < %s | FileCheck %s
+; RUN: opt -hexagon-loop-idiom -S < %s | FileCheck %s
+; RUN: opt -p hexagon-loop-idiom -S < %s | FileCheck %s
; REQUIRES: asserts
;
; Check for sane output, this used to crash.
diff --git a/llvm/test/CodeGen/Hexagon/vcombine_zero_
diff _ptrs.ll b/llvm/test/CodeGen/Hexagon/vcombine_zero_
diff _ptrs.ll
index 2e4243340c12e6..2fba0ce61f46e5 100644
--- a/llvm/test/CodeGen/Hexagon/vcombine_zero_
diff _ptrs.ll
+++ b/llvm/test/CodeGen/Hexagon/vcombine_zero_
diff _ptrs.ll
@@ -1,4 +1,4 @@
-; RUN: opt -march=hexagon -hexagon-vc -S < %s | FileCheck %s
+; RUN: opt -hexagon-vc -S < %s | FileCheck %s
; Test that the HexagonVectorCombine pass identifies instruction
; pairs whose
diff erence in pointers is zero. This creates a vector
diff --git a/llvm/test/CodeGen/Lanai/delay_filler.ll b/llvm/test/CodeGen/Lanai/delay_filler.ll
index bb74276d46de34..88f329d0412953 100644
--- a/llvm/test/CodeGen/Lanai/delay_filler.ll
+++ b/llvm/test/CodeGen/Lanai/delay_filler.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=lanai < %s | FileCheck %s
-; RUN: llc -march=lanai --lanai-nop-delay-filler < %s | \
+; RUN: llc < %s | FileCheck %s
+; RUN: llc --lanai-nop-delay-filler < %s | \
; RUN: FileCheck %s --check-prefix=NOP
; CHECK: bt f
diff --git a/llvm/test/CodeGen/Lanai/lowering-128.ll b/llvm/test/CodeGen/Lanai/lowering-128.ll
index 98fb5ece65c0b2..85a859cb6f1813 100644
--- a/llvm/test/CodeGen/Lanai/lowering-128.ll
+++ b/llvm/test/CodeGen/Lanai/lowering-128.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=lanai < %s | FileCheck %s
+; RUN: llc < %s | FileCheck %s
; Tests that lowering wide registers (128 bits or more) works on Lanai.
; The emitted assembly is not checked, we just do a smoketest.
diff --git a/llvm/test/CodeGen/NVPTX/surf-read.ll b/llvm/test/CodeGen/NVPTX/surf-read.ll
index 1976fcfc00470f..e0cebd60d7dd09 100644
--- a/llvm/test/CodeGen/NVPTX/surf-read.ll
+++ b/llvm/test/CodeGen/NVPTX/surf-read.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
-; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
+; RUN: llc < %s -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
-target triple = "nvptx-unknown-nvcl"
+target triple = "nvptx64-unknown-nvcl"
declare i32 @llvm.nvvm.suld.1d.i32.trap(i64, i32)
diff --git a/llvm/test/CodeGen/NVPTX/surf-write.ll b/llvm/test/CodeGen/NVPTX/surf-write.ll
index 3948b7194ffc04..a3207777cf4c1a 100644
--- a/llvm/test/CodeGen/NVPTX/surf-write.ll
+++ b/llvm/test/CodeGen/NVPTX/surf-write.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
-; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
+; RUN: llc < %s -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
target triple = "nvptx-unknown-nvcl"
diff --git a/llvm/test/CodeGen/NVPTX/tex-read.ll b/llvm/test/CodeGen/NVPTX/tex-read.ll
index 8f6e0416beded9..d11aea45a65f0e 100644
--- a/llvm/test/CodeGen/NVPTX/tex-read.ll
+++ b/llvm/test/CodeGen/NVPTX/tex-read.ll
@@ -1,7 +1,7 @@
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
-; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
+; RUN: llc < %s -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -mcpu=sm_20 -verify-machineinstrs | %ptxas-verify %}
-target triple = "nvptx-unknown-nvcl"
+target triple = "nvptx64-unknown-nvcl"
declare { float, float, float, float } @llvm.nvvm.tex.1d.v4f32.s32(i64, i64, i32)
diff --git a/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll b/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll
index eba481e3345dd2..1fb2cbe5fb5062 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64le-aggregates.ll
@@ -8,7 +8,7 @@
; Currently VSX support is disabled for this test because we generate lxsdx
; instead of lfd, and stxsdx instead of stfd. That is a poor choice when we
; have reg+imm addressing, and is on the list of things to be fixed.
-; The second run step is to ensure that -march=ppc64le is adequate to select
+; The second run step is to ensure that is adequate to select
; the same feature set as with -mcpu=pwr8 since that is the baseline for ppc64le.
target datalayout = "e-m:e-i64:64-n32:64"
diff --git a/llvm/test/CodeGen/Thumb2/bug-subw.ll b/llvm/test/CodeGen/Thumb2/bug-subw.ll
index 41d96116c67ac5..af766fd536da11 100644
--- a/llvm/test/CodeGen/Thumb2/bug-subw.ll
+++ b/llvm/test/CodeGen/Thumb2/bug-subw.ll
@@ -1,5 +1,5 @@
; pr23772 - [ARM] r226200 can emit illegal thumb2 instruction: "sub sp, r12, #80"
-; RUN: llc -march=thumb -mcpu=cortex-m3 -O3 -filetype=asm -o - %s | FileCheck %s
+; RUN: llc -mcpu=cortex-m3 -O3 -filetype=asm -o - %s | FileCheck %s
; CHECK-NOT: sub{{.*}} sp, r{{.*}}, #
; CHECK: .fnend
; TODO: Missed optimization. The three instructions generated to subtract SP can be converged to a single one
diff --git a/llvm/test/DebugInfo/NVPTX/debug-ptx-symbols.ll b/llvm/test/DebugInfo/NVPTX/debug-ptx-symbols.ll
index 99c9773e27f4e0..fe1933ad16fe24 100644
--- a/llvm/test/DebugInfo/NVPTX/debug-ptx-symbols.ll
+++ b/llvm/test/DebugInfo/NVPTX/debug-ptx-symbols.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_60 | FileCheck %s
-; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_60 | %ptxas-verify %}
+; RUN: llc < %s -mcpu=sm_60 | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -mcpu=sm_60 | %ptxas-verify %}
target datalayout = "e-i64:64-i128:128-v16:16-v32:32-n16:32:64"
target triple = "nvptx64-nvidia-cuda"
diff --git a/llvm/test/DebugInfo/X86/instr-ref-flag.ll b/llvm/test/DebugInfo/X86/instr-ref-flag.ll
index 34f22a728e2d03..3f531afd4094bc 100644
--- a/llvm/test/DebugInfo/X86/instr-ref-flag.ll
+++ b/llvm/test/DebugInfo/X86/instr-ref-flag.ll
@@ -1,10 +1,10 @@
-; RUN: llc %s -o - -stop-before=finalize-isel -march=x86-64 \
+; RUN: llc %s -o - -stop-before=finalize-isel \
; RUN: | FileCheck %s --check-prefixes=INSTRREFON
-; RUN: llc %s -o - -stop-before=finalize-isel -march=x86-64 \
+; RUN: llc %s -o - -stop-before=finalize-isel \
; RUN: -experimental-debug-variable-locations=true \
; RUN: | FileCheck %s --check-prefixes=INSTRREFON
-; RUN: llc %s -o - -stop-before=finalize-isel -march=x86-64 \
+; RUN: llc %s -o - -stop-before=finalize-isel \
; RUN: -experimental-debug-variable-locations=false \
; RUN: | FileCheck %s --check-prefixes=INSTRREFOFF \
; RUN: --implicit-check-not=DBG_INSTR_REF
diff --git a/llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll b/llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll
index e4aaad24a07204..4659e630024db2 100644
--- a/llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll
+++ b/llvm/test/DebugInfo/X86/no-entry-values-with-O0.ll
@@ -1,10 +1,10 @@
-; RUN: llc -O0 -dwarf-version=5 -debugger-tune=lldb -march=x86-64 -filetype=obj < %s \
+; RUN: llc -O0 -dwarf-version=5 -debugger-tune=lldb -filetype=obj < %s \
; RUN: | llvm-dwarfdump - | FileCheck --implicit-check-not=DW_OP_entry_value %s
-; RUN: llc -O0 -dwarf-version=5 -debugger-tune=gdb -march=x86-64 -filetype=obj < %s \
+; RUN: llc -O0 -dwarf-version=5 -debugger-tune=gdb -filetype=obj < %s \
; RUN: | llvm-dwarfdump - | FileCheck --implicit-check-not=DW_OP_entry_value %s
-; RUN: llc -force-instr-ref-livedebugvalues=1 -O0 -dwarf-version=5 -debugger-tune=lldb -march=x86-64 -filetype=obj < %s \
+; RUN: llc -force-instr-ref-livedebugvalues=1 -O0 -dwarf-version=5 -debugger-tune=lldb -filetype=obj < %s \
; RUN: | llvm-dwarfdump - | FileCheck --implicit-check-not=DW_OP_entry_value %s
-; RUN: llc -force-instr-ref-livedebugvalues=1 -O0 -dwarf-version=5 -debugger-tune=gdb -march=x86-64 -filetype=obj < %s \
+; RUN: llc -force-instr-ref-livedebugvalues=1 -O0 -dwarf-version=5 -debugger-tune=gdb -filetype=obj < %s \
; RUN: | llvm-dwarfdump - | FileCheck --implicit-check-not=DW_OP_entry_value %s
; The call-site-params are created iff corresponding DISubprogram contains
diff --git a/llvm/test/DebugInfo/X86/single-dbg_value.ll b/llvm/test/DebugInfo/X86/single-dbg_value.ll
index 102d96d0e0a4f1..2dfc2d010f987d 100644
--- a/llvm/test/DebugInfo/X86/single-dbg_value.ll
+++ b/llvm/test/DebugInfo/X86/single-dbg_value.ll
@@ -1,6 +1,6 @@
; RUN: llc -stop-after=livedebugvalues -o - %s \
; RUN: | FileCheck %s --check-prefix=SANITY
-; RUN: llc -march=x86-64 -o - %s -filetype=obj \
+; RUN: llc -o - %s -filetype=obj \
; RUN: | llvm-dwarfdump -v -all - | FileCheck %s
;
; CHECK: .debug_info contents:
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/propagate-invariance-metadata.ll b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/propagate-invariance-metadata.ll
index 4da4ee49f29f24..f2d4ea20230d72 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/propagate-invariance-metadata.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/NVPTX/propagate-invariance-metadata.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=load-store-vectorizer -march=nvptx64 -mcpu=sm_35 -S < %s | FileCheck %s
+; RUN: opt -passes=load-store-vectorizer -mcpu=sm_35 -S < %s | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
target triple = "nvptx64-nvidia-cuda"
diff --git a/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll b/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll
index 916f3b32887b98..9fb50f39dc0ef0 100644
--- a/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll
+++ b/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/reassociate-geps-and-slsr.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
; RUN: opt < %s -passes=separate-const-offset-from-gep,slsr,gvn -S | FileCheck %s
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 | FileCheck %s --check-prefix=PTX
+; RUN: llc < %s -mcpu=sm_35 | FileCheck %s --check-prefix=PTX
target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
target triple = "nvptx64-unknown-unknown"
diff --git a/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/speculative-slsr.ll b/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/speculative-slsr.ll
index 9fe94d6fd3b3ef..92766d5a11aa5d 100644
--- a/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/speculative-slsr.ll
+++ b/llvm/test/Transforms/StraightLineStrengthReduce/NVPTX/speculative-slsr.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 | FileCheck %s
+; RUN: llc < %s -mcpu=sm_35 | FileCheck %s
target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
target triple = "nvptx64-nvidia-cuda"
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