[llvm] 9ef1d37 - [AVR,test] Change llc -march= to -mtriple=
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 15 10:26:38 PST 2024
Author: Fangrui Song
Date: 2024-12-15T10:26:33-08:00
New Revision: 9ef1d37ffb5f56a9b949a6307bbb16c2ea0130e3
URL: https://github.com/llvm/llvm-project/commit/9ef1d37ffb5f56a9b949a6307bbb16c2ea0130e3
DIFF: https://github.com/llvm/llvm-project/commit/9ef1d37ffb5f56a9b949a6307bbb16c2ea0130e3.diff
LOG: [AVR,test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple, leaving a target triple which
may not make sense.
Therefore, -march= is error-prone and not recommended for tests without a target
triple. The issue has been benign as we recognize avr-apple-darwin as ELF instead
of rejecting it outrightly.
Added:
Modified:
llvm/test/CodeGen/AVR/PR31344.ll
llvm/test/CodeGen/AVR/PR31345.ll
llvm/test/CodeGen/AVR/PR37143.ll
llvm/test/CodeGen/AVR/add.ll
llvm/test/CodeGen/AVR/alloca.ll
llvm/test/CodeGen/AVR/and.ll
llvm/test/CodeGen/AVR/atomics/fence.ll
llvm/test/CodeGen/AVR/atomics/load-store-16-unexpected-register-bug.ll
llvm/test/CodeGen/AVR/atomics/load16.ll
llvm/test/CodeGen/AVR/atomics/load32.ll
llvm/test/CodeGen/AVR/atomics/load64.ll
llvm/test/CodeGen/AVR/atomics/load8.ll
llvm/test/CodeGen/AVR/atomics/store.ll
llvm/test/CodeGen/AVR/atomics/store16.ll
llvm/test/CodeGen/AVR/atomics/swap.ll
llvm/test/CodeGen/AVR/avr-rust-issue-123.ll
llvm/test/CodeGen/AVR/block-address-is-in-progmem-space.ll
llvm/test/CodeGen/AVR/branch-relaxation-long.ll
llvm/test/CodeGen/AVR/branch-relaxation.ll
llvm/test/CodeGen/AVR/brind.ll
llvm/test/CodeGen/AVR/calling-conv/c/call.ll
llvm/test/CodeGen/AVR/calling-conv/c/call_aggr.ll
llvm/test/CodeGen/AVR/calling-conv/c/return.ll
llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll
llvm/test/CodeGen/AVR/clear-bss.ll
llvm/test/CodeGen/AVR/cmp.ll
llvm/test/CodeGen/AVR/copy-data-to-ram.ll
llvm/test/CodeGen/AVR/ctlz.ll
llvm/test/CodeGen/AVR/ctpop.ll
llvm/test/CodeGen/AVR/cttz.ll
llvm/test/CodeGen/AVR/directmem.ll
llvm/test/CodeGen/AVR/div.ll
llvm/test/CodeGen/AVR/dynalloca.ll
llvm/test/CodeGen/AVR/eor.ll
llvm/test/CodeGen/AVR/expand-integer-failure.ll
llvm/test/CodeGen/AVR/features/avr25.ll
llvm/test/CodeGen/AVR/features/xmega_io.ll
llvm/test/CodeGen/AVR/frame.ll
llvm/test/CodeGen/AVR/frmidx-iterator-bug.ll
llvm/test/CodeGen/AVR/high-pressure-on-ptrregs.ll
llvm/test/CodeGen/AVR/icall-func-pointer-correct-addr-space.ll
llvm/test/CodeGen/AVR/impossible-reg-to-reg-copy.ll
llvm/test/CodeGen/AVR/inline-asm/inline-asm.ll
llvm/test/CodeGen/AVR/inline-asm/inline-asm2.ll
llvm/test/CodeGen/AVR/integration/blink.ll
llvm/test/CodeGen/AVR/interrupts.ll
llvm/test/CodeGen/AVR/intrinsics/named-reg-alloc.ll
llvm/test/CodeGen/AVR/intrinsics/named-reg-special.ll
llvm/test/CodeGen/AVR/intrinsics/stacksave-restore.ll
llvm/test/CodeGen/AVR/io.ll
llvm/test/CodeGen/AVR/issue-cannot-select-bswap.ll
llvm/test/CodeGen/AVR/issue-regalloc-stackframe-folding-earlyclobber.ll
llvm/test/CodeGen/AVR/large-return-size.ll
llvm/test/CodeGen/AVR/ldd-immediate-overflow.ll
llvm/test/CodeGen/AVR/load.ll
llvm/test/CodeGen/AVR/lower-formal-args-struct-return.ll
llvm/test/CodeGen/AVR/lower-formal-arguments-assertion.ll
llvm/test/CodeGen/AVR/no-clear-bss.ll
llvm/test/CodeGen/AVR/no-copy-data.ll
llvm/test/CodeGen/AVR/no-print-operand-twice.ll
llvm/test/CodeGen/AVR/or.ll
llvm/test/CodeGen/AVR/pre-schedule.ll
llvm/test/CodeGen/AVR/progmem-extended.ll
llvm/test/CodeGen/AVR/progmem.ll
llvm/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir
llvm/test/CodeGen/AVR/rem.ll
llvm/test/CodeGen/AVR/runtime-trig.ll
llvm/test/CodeGen/AVR/rust-avr-bug-112.ll
llvm/test/CodeGen/AVR/rust-avr-bug-37.ll
llvm/test/CodeGen/AVR/rust-avr-bug-95.ll
llvm/test/CodeGen/AVR/rust-avr-bug-99.ll
llvm/test/CodeGen/AVR/rust-bug-98167.ll
llvm/test/CodeGen/AVR/select-must-add-unconditional-jump.ll
llvm/test/CodeGen/AVR/sext.ll
llvm/test/CodeGen/AVR/shift.ll
llvm/test/CodeGen/AVR/sign-extension.ll
llvm/test/CodeGen/AVR/smul-with-overflow.ll
llvm/test/CodeGen/AVR/software-mul.ll
llvm/test/CodeGen/AVR/std-immediate-overflow.ll
llvm/test/CodeGen/AVR/std-ldd-immediate-overflow.ll
llvm/test/CodeGen/AVR/stdwstk.ll
llvm/test/CodeGen/AVR/store-undef.ll
llvm/test/CodeGen/AVR/store.ll
llvm/test/CodeGen/AVR/sub.ll
llvm/test/CodeGen/AVR/trunc.ll
llvm/test/CodeGen/AVR/umul-with-overflow.ll
llvm/test/CodeGen/AVR/umul.with.overflow.i16-bug.ll
llvm/test/CodeGen/AVR/unaligned-atomic-ops.ll
llvm/test/CodeGen/AVR/varargs.ll
llvm/test/CodeGen/AVR/xor.ll
llvm/test/CodeGen/AVR/zeroreg.ll
llvm/test/CodeGen/AVR/zext.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AVR/PR31344.ll b/llvm/test/CodeGen/AVR/PR31344.ll
index 1e7bdb1370fdbc..276adade3bd650 100644
--- a/llvm/test/CodeGen/AVR/PR31344.ll
+++ b/llvm/test/CodeGen/AVR/PR31344.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
; Unit test for: PR 31344
diff --git a/llvm/test/CodeGen/AVR/PR31345.ll b/llvm/test/CodeGen/AVR/PR31345.ll
index 0d69fbc82ce397..70486a0636e279 100644
--- a/llvm/test/CodeGen/AVR/PR31345.ll
+++ b/llvm/test/CodeGen/AVR/PR31345.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
; Unit test for: PR 31345
diff --git a/llvm/test/CodeGen/AVR/PR37143.ll b/llvm/test/CodeGen/AVR/PR37143.ll
index 95ae209aae9506..ab2312d146b0e9 100644
--- a/llvm/test/CodeGen/AVR/PR37143.ll
+++ b/llvm/test/CodeGen/AVR/PR37143.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6,sram < %s -march=avr -verify-machineinstrs | FileCheck %s
+; RUN: llc -mattr=avr6,sram < %s -mtriple=avr -verify-machineinstrs | FileCheck %s
; CHECK: ld {{r[0-9]+}}, [[PTR:[XYZ]]]
; CHECK: ldd {{r[0-9]+}}, [[PTR]]+1
diff --git a/llvm/test/CodeGen/AVR/add.ll b/llvm/test/CodeGen/AVR/add.ll
index 30f23b19937127..ae1c794d9635ba 100644
--- a/llvm/test/CodeGen/AVR/add.ll
+++ b/llvm/test/CodeGen/AVR/add.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=addsubiw < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=addsubiw < %s -mtriple=avr | FileCheck %s
define i8 @add8_reg_reg(i8 %a, i8 %b) {
; CHECK-LABEL: add8_reg_reg:
diff --git a/llvm/test/CodeGen/AVR/alloca.ll b/llvm/test/CodeGen/AVR/alloca.ll
index 2d53106b5f846e..d8b1aeb8b0efe6 100644
--- a/llvm/test/CodeGen/AVR/alloca.ll
+++ b/llvm/test/CodeGen/AVR/alloca.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr -mattr=avr6 | FileCheck %s
+; RUN: llc < %s -mtriple=avr -mattr=avr6 | FileCheck %s
declare i16 @allocate(ptr, ptr)
diff --git a/llvm/test/CodeGen/AVR/and.ll b/llvm/test/CodeGen/AVR/and.ll
index de5bdf992845e9..b537a207926999 100644
--- a/llvm/test/CodeGen/AVR/and.ll
+++ b/llvm/test/CodeGen/AVR/and.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
define i8 @and8_reg_reg(i8 %a, i8 %b) {
; CHECK-LABEL: and8_reg_reg:
diff --git a/llvm/test/CodeGen/AVR/atomics/fence.ll b/llvm/test/CodeGen/AVR/atomics/fence.ll
index 4a0701bcff9bcb..a1eaa5e3033168 100644
--- a/llvm/test/CodeGen/AVR/atomics/fence.ll
+++ b/llvm/test/CodeGen/AVR/atomics/fence.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6 < %s -mtriple=avr | FileCheck %s
; Checks that atomic fences are simply removed from IR.
; AVR is always singlethreaded so fences do nothing.
diff --git a/llvm/test/CodeGen/AVR/atomics/load-store-16-unexpected-register-bug.ll b/llvm/test/CodeGen/AVR/atomics/load-store-16-unexpected-register-bug.ll
index 1f5a61148147c7..a0bf188ba70e4c 100644
--- a/llvm/test/CodeGen/AVR/atomics/load-store-16-unexpected-register-bug.ll
+++ b/llvm/test/CodeGen/AVR/atomics/load-store-16-unexpected-register-bug.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
; At one point, the 16-vit atomic load/store operations we defined in TableGen
; to use 'PTRREGS', but the pseudo expander would generate LDDW/STDW instructions.
diff --git a/llvm/test/CodeGen/AVR/atomics/load16.ll b/llvm/test/CodeGen/AVR/atomics/load16.ll
index 5355fb610a35d5..3e7a61f594540c 100644
--- a/llvm/test/CodeGen/AVR/atomics/load16.ll
+++ b/llvm/test/CodeGen/AVR/atomics/load16.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6 < %s -mtriple=avr | FileCheck %s
; CHECK-LABEL: atomic_load16
; CHECK: in r0, 63
diff --git a/llvm/test/CodeGen/AVR/atomics/load32.ll b/llvm/test/CodeGen/AVR/atomics/load32.ll
index 51a99f1f0e4579..832fd4ad633d37 100644
--- a/llvm/test/CodeGen/AVR/atomics/load32.ll
+++ b/llvm/test/CodeGen/AVR/atomics/load32.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6 < %s -mtriple=avr | FileCheck %s
; CHECK-LABEL: atomic_load32
; CHECK: call __sync_val_compare_and_swap_4
diff --git a/llvm/test/CodeGen/AVR/atomics/load64.ll b/llvm/test/CodeGen/AVR/atomics/load64.ll
index 7fafcb7d35c3d2..5c44d8902ba551 100644
--- a/llvm/test/CodeGen/AVR/atomics/load64.ll
+++ b/llvm/test/CodeGen/AVR/atomics/load64.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6 < %s -mtriple=avr | FileCheck %s
; CHECK-LABEL: atomic_load64
; CHECK: call __sync_val_compare_and_swap_8
diff --git a/llvm/test/CodeGen/AVR/atomics/load8.ll b/llvm/test/CodeGen/AVR/atomics/load8.ll
index 73187a09316a44..00a13080899773 100644
--- a/llvm/test/CodeGen/AVR/atomics/load8.ll
+++ b/llvm/test/CodeGen/AVR/atomics/load8.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6 < %s -mtriple=avr | FileCheck %s
; Tests atomic operations on AVR
diff --git a/llvm/test/CodeGen/AVR/atomics/store.ll b/llvm/test/CodeGen/AVR/atomics/store.ll
index 16a4598347dd70..41a71afacdffc6 100644
--- a/llvm/test/CodeGen/AVR/atomics/store.ll
+++ b/llvm/test/CodeGen/AVR/atomics/store.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6 < %s -mtriple=avr | FileCheck %s
; CHECK-LABEL: atomic_store8
; CHECK: in r0, 63
diff --git a/llvm/test/CodeGen/AVR/atomics/store16.ll b/llvm/test/CodeGen/AVR/atomics/store16.ll
index 05cd865bf85087..6781d4287631d5 100644
--- a/llvm/test/CodeGen/AVR/atomics/store16.ll
+++ b/llvm/test/CodeGen/AVR/atomics/store16.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6 < %s -mtriple=avr | FileCheck %s
; CHECK-LABEL: atomic_store16
; CHECK: in r0, 63
diff --git a/llvm/test/CodeGen/AVR/atomics/swap.ll b/llvm/test/CodeGen/AVR/atomics/swap.ll
index d6eba95949d575..f0eb36096f1429 100644
--- a/llvm/test/CodeGen/AVR/atomics/swap.ll
+++ b/llvm/test/CodeGen/AVR/atomics/swap.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6 < %s -mtriple=avr | FileCheck %s
; CHECK-LABEL: atomic_swap8
; CHECK: call __sync_lock_test_and_set_1
diff --git a/llvm/test/CodeGen/AVR/avr-rust-issue-123.ll b/llvm/test/CodeGen/AVR/avr-rust-issue-123.ll
index c12377bd0756c9..bad0485d67cd9d 100644
--- a/llvm/test/CodeGen/AVR/avr-rust-issue-123.ll
+++ b/llvm/test/CodeGen/AVR/avr-rust-issue-123.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O1 < %s -march=avr | FileCheck %s
+; RUN: llc -O1 < %s -mtriple=avr | FileCheck %s
; This test ensures that the Select8/Select16 expansion
; pass inserts an unconditional branch to the previous adjacent
diff --git a/llvm/test/CodeGen/AVR/block-address-is-in-progmem-space.ll b/llvm/test/CodeGen/AVR/block-address-is-in-progmem-space.ll
index 7b2f25d1bc1cfc..6444c5c30fbe21 100644
--- a/llvm/test/CodeGen/AVR/block-address-is-in-progmem-space.ll
+++ b/llvm/test/CodeGen/AVR/block-address-is-in-progmem-space.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=atmega328 < %s -march=avr | FileCheck %s
+; RUN: llc -mcpu=atmega328 < %s -mtriple=avr | FileCheck %s
; This test verifies that the pointer to a basic block
; should always be a pointer in address space 1.
diff --git a/llvm/test/CodeGen/AVR/branch-relaxation-long.ll b/llvm/test/CodeGen/AVR/branch-relaxation-long.ll
index bca505e5edd5f1..cd7a8046152e97 100644
--- a/llvm/test/CodeGen/AVR/branch-relaxation-long.ll
+++ b/llvm/test/CodeGen/AVR/branch-relaxation-long.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=avr -mattr=avr3 | FileCheck %s
-; RUN: llc < %s -march=avr -mattr=avr2 | FileCheck --check-prefix=AVR2 %s
+; RUN: llc < %s -mtriple=avr -mattr=avr3 | FileCheck %s
+; RUN: llc < %s -mtriple=avr -mattr=avr2 | FileCheck --check-prefix=AVR2 %s
; CHECK-LABEL: relax_to_jmp:
; CHECK: cpi r{{[0-9]+}}, 0
diff --git a/llvm/test/CodeGen/AVR/branch-relaxation.ll b/llvm/test/CodeGen/AVR/branch-relaxation.ll
index 3958cca8f20758..3368ffd3119f40 100644
--- a/llvm/test/CodeGen/AVR/branch-relaxation.ll
+++ b/llvm/test/CodeGen/AVR/branch-relaxation.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=avr | FileCheck %s
-; RUN: llc < %s -march=avr -mcpu=avr5 | FileCheck -check-prefix=AVR5 %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr -mcpu=avr5 | FileCheck -check-prefix=AVR5 %s
; CHECK-LABEL: relax_breq
; CHECK: cpi r{{[0-9]+}}, 0
diff --git a/llvm/test/CodeGen/AVR/brind.ll b/llvm/test/CodeGen/AVR/brind.ll
index 725afd45b4ddfe..7878138d16fc8d 100644
--- a/llvm/test/CodeGen/AVR/brind.ll
+++ b/llvm/test/CodeGen/AVR/brind.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=sram,eijmpcall < %s -march=avr -verify-machineinstrs | FileCheck %s
+; RUN: llc -mattr=sram,eijmpcall < %s -mtriple=avr -verify-machineinstrs | FileCheck %s
@brind.k = private unnamed_addr constant [2 x ptr addrspace(1)] [ptr addrspace(1) blockaddress(@brind, %return), ptr addrspace(1) blockaddress(@brind, %b)], align 1
diff --git a/llvm/test/CodeGen/AVR/calling-conv/c/call.ll b/llvm/test/CodeGen/AVR/calling-conv/c/call.ll
index e218ed37238a35..28bfdca507bf69 100644
--- a/llvm/test/CodeGen/AVR/calling-conv/c/call.ll
+++ b/llvm/test/CodeGen/AVR/calling-conv/c/call.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
declare void @ret_void_args_i8(i8 %a)
declare void @ret_void_args_i8_i32(i8 %a, i32 %b)
diff --git a/llvm/test/CodeGen/AVR/calling-conv/c/call_aggr.ll b/llvm/test/CodeGen/AVR/calling-conv/c/call_aggr.ll
index aeba3c8f9757a5..5c9d0a80babc6e 100644
--- a/llvm/test/CodeGen/AVR/calling-conv/c/call_aggr.ll
+++ b/llvm/test/CodeGen/AVR/calling-conv/c/call_aggr.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
declare void @ret_void_args_struct_i8_i32({ i8, i32 } %a)
declare void @ret_void_args_struct_i8_i8_i8_i8({ i8, i8, i8, i8 } %a)
diff --git a/llvm/test/CodeGen/AVR/calling-conv/c/return.ll b/llvm/test/CodeGen/AVR/calling-conv/c/return.ll
index 1d240b85a19d61..934a62c7618e73 100644
--- a/llvm/test/CodeGen/AVR/calling-conv/c/return.ll
+++ b/llvm/test/CodeGen/AVR/calling-conv/c/return.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
; CHECK-LABEL: ret_i8
define i8 @ret_i8() {
diff --git a/llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll b/llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll
index 97668f6c05733a..6f154a9afffaea 100644
--- a/llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll
+++ b/llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
; CHECK-LABEL: ret_struct_i8_i16_i8
define { i8, i16, i8 } @ret_struct_i8_i16_i8() {
diff --git a/llvm/test/CodeGen/AVR/clear-bss.ll b/llvm/test/CodeGen/AVR/clear-bss.ll
index a822610bea7d3f..e590e6177e890e 100644
--- a/llvm/test/CodeGen/AVR/clear-bss.ll
+++ b/llvm/test/CodeGen/AVR/clear-bss.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
; CHECK: .globl __do_clear_bss
@zeroed = internal global [3 x i8] zeroinitializer
diff --git a/llvm/test/CodeGen/AVR/cmp.ll b/llvm/test/CodeGen/AVR/cmp.ll
index 715a3f1c9c18e3..efc9b8da45ba53 100644
--- a/llvm/test/CodeGen/AVR/cmp.ll
+++ b/llvm/test/CodeGen/AVR/cmp.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
; RUN: llc < %s -mtriple=avr -mcpu=attiny10 | FileCheck --check-prefix=TINY %s
declare void @f1(i8)
diff --git a/llvm/test/CodeGen/AVR/copy-data-to-ram.ll b/llvm/test/CodeGen/AVR/copy-data-to-ram.ll
index 021cc0f1a7f4fc..a91dd55841cebc 100644
--- a/llvm/test/CodeGen/AVR/copy-data-to-ram.ll
+++ b/llvm/test/CodeGen/AVR/copy-data-to-ram.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
; CHECK: .globl __do_copy_data
@str = internal global [3 x i8] c"foo"
diff --git a/llvm/test/CodeGen/AVR/ctlz.ll b/llvm/test/CodeGen/AVR/ctlz.ll
index 93c2f0bdfa41e9..69ceca35da7f80 100644
--- a/llvm/test/CodeGen/AVR/ctlz.ll
+++ b/llvm/test/CodeGen/AVR/ctlz.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
define i8 @count_leading_zeros(i8) unnamed_addr {
entry-block:
diff --git a/llvm/test/CodeGen/AVR/ctpop.ll b/llvm/test/CodeGen/AVR/ctpop.ll
index 4fea540da43128..54a6a35f821715 100644
--- a/llvm/test/CodeGen/AVR/ctpop.ll
+++ b/llvm/test/CodeGen/AVR/ctpop.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
define i8 @count_population(i8) unnamed_addr {
entry-block:
diff --git a/llvm/test/CodeGen/AVR/cttz.ll b/llvm/test/CodeGen/AVR/cttz.ll
index b1ef34acf63158..9f1680a71f1d24 100644
--- a/llvm/test/CodeGen/AVR/cttz.ll
+++ b/llvm/test/CodeGen/AVR/cttz.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
define i8 @count_trailing_zeros(i8) unnamed_addr {
entry-block:
diff --git a/llvm/test/CodeGen/AVR/directmem.ll b/llvm/test/CodeGen/AVR/directmem.ll
index c3b5e1f528fbad..cecabf4f549c19 100644
--- a/llvm/test/CodeGen/AVR/directmem.ll
+++ b/llvm/test/CodeGen/AVR/directmem.ll
@@ -1,5 +1,5 @@
-; RUN: llc -mattr=sram,addsubiw < %s -march=avr | FileCheck %s
-; RUN: llc -mattr=sram,avrtiny < %s -march=avr | FileCheck %s --check-prefix=CHECK-TINY
+; RUN: llc -mattr=sram,addsubiw < %s -mtriple=avr | FileCheck %s
+; RUN: llc -mattr=sram,avrtiny < %s -mtriple=avr | FileCheck %s --check-prefix=CHECK-TINY
@char = common global i8 0
@char.array = common global [3 x i8] zeroinitializer
diff --git a/llvm/test/CodeGen/AVR/div.ll b/llvm/test/CodeGen/AVR/div.ll
index b22229421963ba..5e336039f67297 100644
--- a/llvm/test/CodeGen/AVR/div.ll
+++ b/llvm/test/CodeGen/AVR/div.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=mul,movw < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=mul,movw < %s -mtriple=avr | FileCheck %s
; Unsigned 8-bit division
define i8 @udiv8(i8 %a, i8 %b) {
diff --git a/llvm/test/CodeGen/AVR/dynalloca.ll b/llvm/test/CodeGen/AVR/dynalloca.ll
index 79fe8b02885f51..774bb76d0a0e0e 100644
--- a/llvm/test/CodeGen/AVR/dynalloca.ll
+++ b/llvm/test/CodeGen/AVR/dynalloca.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
declare void @foo(ptr, ptr, ptr)
diff --git a/llvm/test/CodeGen/AVR/eor.ll b/llvm/test/CodeGen/AVR/eor.ll
index a32bc24a808470..0e8fb1816f3a46 100644
--- a/llvm/test/CodeGen/AVR/eor.ll
+++ b/llvm/test/CodeGen/AVR/eor.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
; Tests for the exclusive OR operation.
diff --git a/llvm/test/CodeGen/AVR/expand-integer-failure.ll b/llvm/test/CodeGen/AVR/expand-integer-failure.ll
index 99be3c8068df3c..5b4101e0ca54a6 100644
--- a/llvm/test/CodeGen/AVR/expand-integer-failure.ll
+++ b/llvm/test/CodeGen/AVR/expand-integer-failure.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
; Causes an assertion error
; Assertion failed: (Lo.getValueType() == TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType()) &&
diff --git a/llvm/test/CodeGen/AVR/features/avr25.ll b/llvm/test/CodeGen/AVR/features/avr25.ll
index f71eb24501c315..963f854d4d3e61 100644
--- a/llvm/test/CodeGen/AVR/features/avr25.ll
+++ b/llvm/test/CodeGen/AVR/features/avr25.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr25 -O0 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr25 -O0 < %s -mtriple=avr | FileCheck %s
; On most cores, the 16-bit 'MOVW' instruction can be used
define i16 @reg_copy16(i16, i16 %a) {
diff --git a/llvm/test/CodeGen/AVR/features/xmega_io.ll b/llvm/test/CodeGen/AVR/features/xmega_io.ll
index 8d0b32b9edbdd4..9e69e6092f4bdc 100644
--- a/llvm/test/CodeGen/AVR/features/xmega_io.ll
+++ b/llvm/test/CodeGen/AVR/features/xmega_io.ll
@@ -1,19 +1,19 @@
-; RUN: llc -O0 < %s -march=avr -mcpu avrxmega1 | FileCheck %s -check-prefix=XMEGA
-; RUN: llc -O0 < %s -march=avr -mcpu avrxmega2 | FileCheck %s -check-prefix=XMEGA
-; RUN: llc -O0 < %s -march=avr -mcpu avrxmega3 | FileCheck %s -check-prefix=XMEGA
-; RUN: llc -O0 < %s -march=avr -mcpu avrxmega4 | FileCheck %s -check-prefix=XMEGA
-; RUN: llc -O0 < %s -march=avr -mcpu avrxmega5 | FileCheck %s -check-prefix=XMEGA
-; RUN: llc -O0 < %s -march=avr -mcpu avrxmega6 | FileCheck %s -check-prefix=XMEGA
-; RUN: llc -O0 < %s -march=avr -mcpu avrxmega7 | FileCheck %s -check-prefix=XMEGA
-; RUN: llc -O0 < %s -march=avr -mcpu avr2 | FileCheck %s -check-prefix=AVR
-; RUN: llc -O0 < %s -march=avr -mcpu avr25 | FileCheck %s -check-prefix=AVR
-; RUN: llc -O0 < %s -march=avr -mcpu avr3 | FileCheck %s -check-prefix=AVR
-; RUN: llc -O0 < %s -march=avr -mcpu avr31 | FileCheck %s -check-prefix=AVR
-; RUN: llc -O0 < %s -march=avr -mcpu avr35 | FileCheck %s -check-prefix=AVR
-; RUN: llc -O0 < %s -march=avr -mcpu avr4 | FileCheck %s -check-prefix=AVR
-; RUN: llc -O0 < %s -march=avr -mcpu avr5 | FileCheck %s -check-prefix=AVR
-; RUN: llc -O0 < %s -march=avr -mcpu avr51 | FileCheck %s -check-prefix=AVR
-; RUN: llc -O0 < %s -march=avr -mcpu avr6 | FileCheck %s -check-prefix=AVR
+; RUN: llc -O0 < %s -mtriple=avr -mcpu avrxmega1 | FileCheck %s -check-prefix=XMEGA
+; RUN: llc -O0 < %s -mtriple=avr -mcpu avrxmega2 | FileCheck %s -check-prefix=XMEGA
+; RUN: llc -O0 < %s -mtriple=avr -mcpu avrxmega3 | FileCheck %s -check-prefix=XMEGA
+; RUN: llc -O0 < %s -mtriple=avr -mcpu avrxmega4 | FileCheck %s -check-prefix=XMEGA
+; RUN: llc -O0 < %s -mtriple=avr -mcpu avrxmega5 | FileCheck %s -check-prefix=XMEGA
+; RUN: llc -O0 < %s -mtriple=avr -mcpu avrxmega6 | FileCheck %s -check-prefix=XMEGA
+; RUN: llc -O0 < %s -mtriple=avr -mcpu avrxmega7 | FileCheck %s -check-prefix=XMEGA
+; RUN: llc -O0 < %s -mtriple=avr -mcpu avr2 | FileCheck %s -check-prefix=AVR
+; RUN: llc -O0 < %s -mtriple=avr -mcpu avr25 | FileCheck %s -check-prefix=AVR
+; RUN: llc -O0 < %s -mtriple=avr -mcpu avr3 | FileCheck %s -check-prefix=AVR
+; RUN: llc -O0 < %s -mtriple=avr -mcpu avr31 | FileCheck %s -check-prefix=AVR
+; RUN: llc -O0 < %s -mtriple=avr -mcpu avr35 | FileCheck %s -check-prefix=AVR
+; RUN: llc -O0 < %s -mtriple=avr -mcpu avr4 | FileCheck %s -check-prefix=AVR
+; RUN: llc -O0 < %s -mtriple=avr -mcpu avr5 | FileCheck %s -check-prefix=AVR
+; RUN: llc -O0 < %s -mtriple=avr -mcpu avr51 | FileCheck %s -check-prefix=AVR
+; RUN: llc -O0 < %s -mtriple=avr -mcpu avr6 | FileCheck %s -check-prefix=AVR
define i8 @read8_low_io() {
; CHECK-LABEL: read8_low_io
diff --git a/llvm/test/CodeGen/AVR/frame.ll b/llvm/test/CodeGen/AVR/frame.ll
index cd997a454dbc10..6223432a8f46ff 100644
--- a/llvm/test/CodeGen/AVR/frame.ll
+++ b/llvm/test/CodeGen/AVR/frame.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=mul < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=mul < %s -mtriple=avr | FileCheck %s
declare float @dsin(float)
declare float @dcos(float)
diff --git a/llvm/test/CodeGen/AVR/frmidx-iterator-bug.ll b/llvm/test/CodeGen/AVR/frmidx-iterator-bug.ll
index 3dfcfc9b99882e..ddf65af8402d9c 100644
--- a/llvm/test/CodeGen/AVR/frmidx-iterator-bug.ll
+++ b/llvm/test/CodeGen/AVR/frmidx-iterator-bug.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr -mattr=avr6 | FileCheck %s
+; RUN: llc < %s -mtriple=avr -mattr=avr6 | FileCheck %s
%str_slice = type { ptr, i16 }
%Machine = type { i16, [0 x i8], i16, [0 x i8], [16 x i8], [0 x i8] }
diff --git a/llvm/test/CodeGen/AVR/high-pressure-on-ptrregs.ll b/llvm/test/CodeGen/AVR/high-pressure-on-ptrregs.ll
index fcc13da8e1e523..c894c4a70e4395 100644
--- a/llvm/test/CodeGen/AVR/high-pressure-on-ptrregs.ll
+++ b/llvm/test/CodeGen/AVR/high-pressure-on-ptrregs.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
; This tests how LLVM handles IR which puts very high
; presure on the PTRREGS class for the register allocator.
diff --git a/llvm/test/CodeGen/AVR/icall-func-pointer-correct-addr-space.ll b/llvm/test/CodeGen/AVR/icall-func-pointer-correct-addr-space.ll
index 51b8f219a26d56..995d884069838e 100644
--- a/llvm/test/CodeGen/AVR/icall-func-pointer-correct-addr-space.ll
+++ b/llvm/test/CodeGen/AVR/icall-func-pointer-correct-addr-space.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=lpm,lpmw < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=lpm,lpmw < %s -mtriple=avr | FileCheck %s
@callbackPtr = common global ptr addrspace(1) null, align 8
@myValuePtr = common global ptr null, align 8
diff --git a/llvm/test/CodeGen/AVR/impossible-reg-to-reg-copy.ll b/llvm/test/CodeGen/AVR/impossible-reg-to-reg-copy.ll
index 770f4d59561528..2d7ea2d5df2f44 100644
--- a/llvm/test/CodeGen/AVR/impossible-reg-to-reg-copy.ll
+++ b/llvm/test/CodeGen/AVR/impossible-reg-to-reg-copy.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
; Test case for an assertion error.
;
diff --git a/llvm/test/CodeGen/AVR/inline-asm/inline-asm.ll b/llvm/test/CodeGen/AVR/inline-asm/inline-asm.ll
index 5c5588b73da471..d19188c76e9e18 100644
--- a/llvm/test/CodeGen/AVR/inline-asm/inline-asm.ll
+++ b/llvm/test/CodeGen/AVR/inline-asm/inline-asm.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr -mattr=movw -no-integrated-as | FileCheck %s
+; RUN: llc < %s -mtriple=avr -mattr=movw -no-integrated-as | FileCheck %s
; XFAIL: *
; CHECK-LABEL: no_operands:
diff --git a/llvm/test/CodeGen/AVR/inline-asm/inline-asm2.ll b/llvm/test/CodeGen/AVR/inline-asm/inline-asm2.ll
index 74365b42c60e5a..ab4219c81f5207 100644
--- a/llvm/test/CodeGen/AVR/inline-asm/inline-asm2.ll
+++ b/llvm/test/CodeGen/AVR/inline-asm/inline-asm2.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr -no-integrated-as | FileCheck %s
+; RUN: llc < %s -mtriple=avr -no-integrated-as | FileCheck %s
; CHECK-LABEL: foo
define void @foo(i16 %a) {
diff --git a/llvm/test/CodeGen/AVR/integration/blink.ll b/llvm/test/CodeGen/AVR/integration/blink.ll
index 6456ffa857d01f..c4149ff90124dd 100644
--- a/llvm/test/CodeGen/AVR/integration/blink.ll
+++ b/llvm/test/CodeGen/AVR/integration/blink.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr -mcpu=atmega328p | FileCheck %s
+; RUN: llc < %s -mtriple=avr -mcpu=atmega328p | FileCheck %s
; This test checks a basic 'blinking led' program.
; It is written for the ATmega328P
diff --git a/llvm/test/CodeGen/AVR/interrupts.ll b/llvm/test/CodeGen/AVR/interrupts.ll
index d344561f86814b..0929a256c19b86 100644
--- a/llvm/test/CodeGen/AVR/interrupts.ll
+++ b/llvm/test/CodeGen/AVR/interrupts.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
@count = global i8 0
@funcptr = global ptr addrspace(1) null
diff --git a/llvm/test/CodeGen/AVR/intrinsics/named-reg-alloc.ll b/llvm/test/CodeGen/AVR/intrinsics/named-reg-alloc.ll
index 33e78ea02e34f8..17d7eda22a1c2b 100644
--- a/llvm/test/CodeGen/AVR/intrinsics/named-reg-alloc.ll
+++ b/llvm/test/CodeGen/AVR/intrinsics/named-reg-alloc.ll
@@ -1,4 +1,4 @@
-; RUN: not --crash llc -O0 < %s -march=avr 2>&1 | FileCheck %s
+; RUN: not --crash llc -O0 < %s -mtriple=avr 2>&1 | FileCheck %s
define void @foo() {
entry:
diff --git a/llvm/test/CodeGen/AVR/intrinsics/named-reg-special.ll b/llvm/test/CodeGen/AVR/intrinsics/named-reg-special.ll
index e215e76f385dc5..66bc295f52b2e5 100644
--- a/llvm/test/CodeGen/AVR/intrinsics/named-reg-special.ll
+++ b/llvm/test/CodeGen/AVR/intrinsics/named-reg-special.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 < %s -march=avr | FileCheck %s
+; RUN: llc -O0 < %s -mtriple=avr | FileCheck %s
; CHECK-LABEL: read_sp:
; CHECK: in r24, 61
diff --git a/llvm/test/CodeGen/AVR/intrinsics/stacksave-restore.ll b/llvm/test/CodeGen/AVR/intrinsics/stacksave-restore.ll
index 5a86831416d7b5..6032950a37d1e6 100644
--- a/llvm/test/CodeGen/AVR/intrinsics/stacksave-restore.ll
+++ b/llvm/test/CodeGen/AVR/intrinsics/stacksave-restore.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 < %s -march=avr | FileCheck %s
+; RUN: llc -O0 < %s -mtriple=avr | FileCheck %s
; CHECK-LABEL: foo
define void @foo() {
diff --git a/llvm/test/CodeGen/AVR/io.ll b/llvm/test/CodeGen/AVR/io.ll
index ba8dd58f9bbef9..f9d57fc8e7c24c 100644
--- a/llvm/test/CodeGen/AVR/io.ll
+++ b/llvm/test/CodeGen/AVR/io.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
define i8 @read8() {
; CHECK-LABEL: read8
diff --git a/llvm/test/CodeGen/AVR/issue-cannot-select-bswap.ll b/llvm/test/CodeGen/AVR/issue-cannot-select-bswap.ll
index bf26e403524df8..4551af14016fbd 100644
--- a/llvm/test/CodeGen/AVR/issue-cannot-select-bswap.ll
+++ b/llvm/test/CodeGen/AVR/issue-cannot-select-bswap.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
declare i16 @llvm.bswap.i16(i16)
diff --git a/llvm/test/CodeGen/AVR/issue-regalloc-stackframe-folding-earlyclobber.ll b/llvm/test/CodeGen/AVR/issue-regalloc-stackframe-folding-earlyclobber.ll
index 9064d62f8995ee..47e9f565bc9e22 100644
--- a/llvm/test/CodeGen/AVR/issue-regalloc-stackframe-folding-earlyclobber.ll
+++ b/llvm/test/CodeGen/AVR/issue-regalloc-stackframe-folding-earlyclobber.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr -mcpu=atmega328 | FileCheck %s
+; RUN: llc < %s -mtriple=avr -mcpu=atmega328 | FileCheck %s
; This test case is designed to trigger a bug caused by the register
; allocator not handling the case where a target generates a load/store with
diff --git a/llvm/test/CodeGen/AVR/large-return-size.ll b/llvm/test/CodeGen/AVR/large-return-size.ll
index 5f51fa1079e5a8..154ae4cae8756d 100644
--- a/llvm/test/CodeGen/AVR/large-return-size.ll
+++ b/llvm/test/CodeGen/AVR/large-return-size.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
define void @call_more_than_64_bits() {
; CHECK-LABEL: call_more_than_64_bits
entry-block:
diff --git a/llvm/test/CodeGen/AVR/ldd-immediate-overflow.ll b/llvm/test/CodeGen/AVR/ldd-immediate-overflow.ll
index 6f1a4b32bb054c..79c901d581e46d 100644
--- a/llvm/test/CodeGen/AVR/ldd-immediate-overflow.ll
+++ b/llvm/test/CodeGen/AVR/ldd-immediate-overflow.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=avr -filetype=asm -O1 < %s | FileCheck %s
+; RUN: llc -mtriple=avr -filetype=asm -O1 < %s | FileCheck %s
define void @check60(ptr %1) {
; CHECK-LABEL: check60:
diff --git a/llvm/test/CodeGen/AVR/load.ll b/llvm/test/CodeGen/AVR/load.ll
index 320ffb34a2c0e0..5de6b486529143 100644
--- a/llvm/test/CodeGen/AVR/load.ll
+++ b/llvm/test/CodeGen/AVR/load.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6,sram < %s -march=avr -verify-machineinstrs | FileCheck %s
+; RUN: llc -mattr=avr6,sram < %s -mtriple=avr -verify-machineinstrs | FileCheck %s
define i8 @load8(ptr %x) {
; CHECK-LABEL: load8:
diff --git a/llvm/test/CodeGen/AVR/lower-formal-args-struct-return.ll b/llvm/test/CodeGen/AVR/lower-formal-args-struct-return.ll
index f7a45632ba83c8..9bcbfebf13af8b 100644
--- a/llvm/test/CodeGen/AVR/lower-formal-args-struct-return.ll
+++ b/llvm/test/CodeGen/AVR/lower-formal-args-struct-return.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
; This test ensures that the backend can lower returns of struct values.
; It does not check how these are lowered.
diff --git a/llvm/test/CodeGen/AVR/lower-formal-arguments-assertion.ll b/llvm/test/CodeGen/AVR/lower-formal-arguments-assertion.ll
index 4c1a5ef939bde0..019177194e053d 100644
--- a/llvm/test/CodeGen/AVR/lower-formal-arguments-assertion.ll
+++ b/llvm/test/CodeGen/AVR/lower-formal-arguments-assertion.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
define void @foo(i1) {
; CHECK-LABEL: foo:
diff --git a/llvm/test/CodeGen/AVR/no-clear-bss.ll b/llvm/test/CodeGen/AVR/no-clear-bss.ll
index 4a257470f8e092..cfe84e61fdb12a 100644
--- a/llvm/test/CodeGen/AVR/no-clear-bss.ll
+++ b/llvm/test/CodeGen/AVR/no-clear-bss.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
; CHECK: .globl __do_copy_data
; CHECK-NOT: .globl __do_clear_bss
diff --git a/llvm/test/CodeGen/AVR/no-copy-data.ll b/llvm/test/CodeGen/AVR/no-copy-data.ll
index 4875296c19aa4b..9771c8ab2d6dee 100644
--- a/llvm/test/CodeGen/AVR/no-copy-data.ll
+++ b/llvm/test/CodeGen/AVR/no-copy-data.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
; CHECK-NOT: .globl __do_copy_data
; CHECK: .globl __do_clear_bss
diff --git a/llvm/test/CodeGen/AVR/no-print-operand-twice.ll b/llvm/test/CodeGen/AVR/no-print-operand-twice.ll
index 8326507768ba4e..e479a3919837b4 100644
--- a/llvm/test/CodeGen/AVR/no-print-operand-twice.ll
+++ b/llvm/test/CodeGen/AVR/no-print-operand-twice.ll
@@ -1,4 +1,4 @@
-; RUN: llc -no-integrated-as -march=avr < %s | FileCheck %s
+; RUN: llc -no-integrated-as -mtriple=avr < %s | FileCheck %s
define void @test() {
entry:
diff --git a/llvm/test/CodeGen/AVR/or.ll b/llvm/test/CodeGen/AVR/or.ll
index 7ffa531feefca7..e12cd9cbf21b5b 100644
--- a/llvm/test/CodeGen/AVR/or.ll
+++ b/llvm/test/CodeGen/AVR/or.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
define i8 @or8_reg_reg(i8 %a, i8 %b) {
; CHECK-LABEL: or8_reg_reg:
diff --git a/llvm/test/CodeGen/AVR/pre-schedule.ll b/llvm/test/CodeGen/AVR/pre-schedule.ll
index c724eea5d36552..a58c5163bf4e73 100644
--- a/llvm/test/CodeGen/AVR/pre-schedule.ll
+++ b/llvm/test/CodeGen/AVR/pre-schedule.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
target triple = "avr-unknown-unknown"
; The case illustrate DAG schedular may pre-schedule the node has
diff --git a/llvm/test/CodeGen/AVR/progmem-extended.ll b/llvm/test/CodeGen/AVR/progmem-extended.ll
index ce2bcc80cc3a90..344b3bcc811be7 100644
--- a/llvm/test/CodeGen/AVR/progmem-extended.ll
+++ b/llvm/test/CodeGen/AVR/progmem-extended.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr -mattr=movw,lpmx | FileCheck %s
+; RUN: llc < %s -mtriple=avr -mattr=movw,lpmx | FileCheck %s
; XFAIL: *
# Wide LPM is currently unimplemented in the pseudo expansion pass.
diff --git a/llvm/test/CodeGen/AVR/progmem.ll b/llvm/test/CodeGen/AVR/progmem.ll
index 40edc1aa6f0d91..4208a155345913 100644
--- a/llvm/test/CodeGen/AVR/progmem.ll
+++ b/llvm/test/CodeGen/AVR/progmem.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr -mattr=movw,lpm | FileCheck %s
+; RUN: llc < %s -mtriple=avr -mattr=movw,lpm | FileCheck %s
; XFAIL: *
; Tests the standard LPM instruction
diff --git a/llvm/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir b/llvm/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir
index 7875cfd5c56511..50221ba18ad11a 100644
--- a/llvm/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir
@@ -1,4 +1,4 @@
-# RUN: llc -O0 %s -o - -march=avr | FileCheck %s
+# RUN: llc -O0 %s -o - -mtriple=avr | FileCheck %s
# This test checks the expansion of the 16-bit 'LDDWRdYQ instruction
diff --git a/llvm/test/CodeGen/AVR/rem.ll b/llvm/test/CodeGen/AVR/rem.ll
index 47573e8dafc536..da7eadc714fb7c 100644
--- a/llvm/test/CodeGen/AVR/rem.ll
+++ b/llvm/test/CodeGen/AVR/rem.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=mul,movw < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=mul,movw < %s -mtriple=avr | FileCheck %s
; Unsigned 8-bit remision
define i8 @urem8(i8 %a, i8 %b) {
diff --git a/llvm/test/CodeGen/AVR/runtime-trig.ll b/llvm/test/CodeGen/AVR/runtime-trig.ll
index 2673dd39576d68..72ae5d20a2ea8f 100644
--- a/llvm/test/CodeGen/AVR/runtime-trig.ll
+++ b/llvm/test/CodeGen/AVR/runtime-trig.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
; Checks that `sin` and `cos` nodes are expanded into calls to
; the `sin` and `cos` runtime library functions.
diff --git a/llvm/test/CodeGen/AVR/rust-avr-bug-112.ll b/llvm/test/CodeGen/AVR/rust-avr-bug-112.ll
index 033ee88d7d9e89..4c748ade14e579 100644
--- a/llvm/test/CodeGen/AVR/rust-avr-bug-112.ll
+++ b/llvm/test/CodeGen/AVR/rust-avr-bug-112.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
; The avr-rust bug can be found here:
; https://github.com/avr-rust/rust/issues/112
diff --git a/llvm/test/CodeGen/AVR/rust-avr-bug-37.ll b/llvm/test/CodeGen/AVR/rust-avr-bug-37.ll
index bb9597f9cabffd..e62d2dffbc8bca 100644
--- a/llvm/test/CodeGen/AVR/rust-avr-bug-37.ll
+++ b/llvm/test/CodeGen/AVR/rust-avr-bug-37.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
%"fmt::Formatter" = type { i32, { ptr, ptr } }
diff --git a/llvm/test/CodeGen/AVR/rust-avr-bug-95.ll b/llvm/test/CodeGen/AVR/rust-avr-bug-95.ll
index 0b9924b02fedae..fc28a73a5541cf 100644
--- a/llvm/test/CodeGen/AVR/rust-avr-bug-95.ll
+++ b/llvm/test/CodeGen/AVR/rust-avr-bug-95.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
%"fmt::Formatter.1.77.153.229.305.381.1673" = type { [0 x i8], i32, [0 x i8], i32, [0 x i8], i8, [0 x i8], %"option::Option<usize>.0.76.152.228.304.380.1672", [0 x i8], %"option::Option<usize>.0.76.152.228.304.380.1672", [0 x i8], { ptr, ptr }, [0 x i8], { ptr, ptr }, [0 x i8], { ptr, i16 }, [0 x i8] }
%"option::Option<usize>.0.76.152.228.304.380.1672" = type { [0 x i8], i8, [2 x i8] }
diff --git a/llvm/test/CodeGen/AVR/rust-avr-bug-99.ll b/llvm/test/CodeGen/AVR/rust-avr-bug-99.ll
index 8620ab3b442bc1..2579e061edb9eb 100644
--- a/llvm/test/CodeGen/AVR/rust-avr-bug-99.ll
+++ b/llvm/test/CodeGen/AVR/rust-avr-bug-99.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr -mcpu=avr5 | FileCheck %s
+; RUN: llc < %s -mtriple=avr -mcpu=avr5 | FileCheck %s
; The original reason for this failure is that the BranchFolderPass disables liveness
; tracking unless you override the trackLivenessAfterRegAlloc function and return true.
diff --git a/llvm/test/CodeGen/AVR/rust-bug-98167.ll b/llvm/test/CodeGen/AVR/rust-bug-98167.ll
index 134623e838ae7e..530c2ac2564245 100644
--- a/llvm/test/CodeGen/AVR/rust-bug-98167.ll
+++ b/llvm/test/CodeGen/AVR/rust-bug-98167.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
; The bug can be found here:
; https://github.com/rust-lang/rust/issues/98167
diff --git a/llvm/test/CodeGen/AVR/select-must-add-unconditional-jump.ll b/llvm/test/CodeGen/AVR/select-must-add-unconditional-jump.ll
index b8536bdc3cb09e..c906392befe695 100644
--- a/llvm/test/CodeGen/AVR/select-must-add-unconditional-jump.ll
+++ b/llvm/test/CodeGen/AVR/select-must-add-unconditional-jump.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=avr -print-after=finalize-isel -cgp-freq-ratio-to-skip-merge=10 < %s 2>&1 | FileCheck %s
+; RUN: llc -mtriple=avr -print-after=finalize-isel -cgp-freq-ratio-to-skip-merge=10 < %s 2>&1 | FileCheck %s
; Because `switch` seems to trigger Machine Basic Blocks to be ordered
; in a
diff erent order than they were constructed, this exposes an
diff --git a/llvm/test/CodeGen/AVR/sext.ll b/llvm/test/CodeGen/AVR/sext.ll
index 7fb6d84ec446c1..4495d1bc26001e 100644
--- a/llvm/test/CodeGen/AVR/sext.ll
+++ b/llvm/test/CodeGen/AVR/sext.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
; sext R17:R16, R13
; mov r16, r13
diff --git a/llvm/test/CodeGen/AVR/shift.ll b/llvm/test/CodeGen/AVR/shift.ll
index 55ea509a8a5b67..9836f93527b3cc 100644
--- a/llvm/test/CodeGen/AVR/shift.ll
+++ b/llvm/test/CodeGen/AVR/shift.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=avr -march=avr -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=avr -mtriple=avr -verify-machineinstrs | FileCheck %s
; Optimize for speed.
define i8 @shift_i8_i8_speed(i8 %a, i8 %b) {
diff --git a/llvm/test/CodeGen/AVR/sign-extension.ll b/llvm/test/CodeGen/AVR/sign-extension.ll
index 116617a9efb3df..1f7fc11dda151b 100644
--- a/llvm/test/CodeGen/AVR/sign-extension.ll
+++ b/llvm/test/CodeGen/AVR/sign-extension.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=avr -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=avr -verify-machineinstrs < %s | FileCheck %s
define i8 @sign_extended_1_to_8(i1) {
; CHECK-LABEL: sign_extended_1_to_8
diff --git a/llvm/test/CodeGen/AVR/smul-with-overflow.ll b/llvm/test/CodeGen/AVR/smul-with-overflow.ll
index cffb84fa0f212f..4206aeb8cf2934 100644
--- a/llvm/test/CodeGen/AVR/smul-with-overflow.ll
+++ b/llvm/test/CodeGen/AVR/smul-with-overflow.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6 < %s -mtriple=avr | FileCheck %s
define i1 @signed_multiplication_did_overflow(i8, i8) unnamed_addr {
; CHECK-LABEL: signed_multiplication_did_overflow:
diff --git a/llvm/test/CodeGen/AVR/software-mul.ll b/llvm/test/CodeGen/AVR/software-mul.ll
index 9a4d28127eb876..0f67e1d84d6a8c 100644
--- a/llvm/test/CodeGen/AVR/software-mul.ll
+++ b/llvm/test/CodeGen/AVR/software-mul.ll
@@ -1,8 +1,8 @@
-; RUN: llc -mattr=avr6,-mul < %s -march=avr | FileCheck %s
-; RUN: llc -mcpu=attiny85 < %s -march=avr | FileCheck %s
-; RUN: llc -mcpu=ata5272 < %s -march=avr | FileCheck %s
-; RUN: llc -mcpu=attiny861a < %s -march=avr | FileCheck %s
-; RUN: llc -mcpu=at90usb82 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6,-mul < %s -mtriple=avr | FileCheck %s
+; RUN: llc -mcpu=attiny85 < %s -mtriple=avr | FileCheck %s
+; RUN: llc -mcpu=ata5272 < %s -mtriple=avr | FileCheck %s
+; RUN: llc -mcpu=attiny861a < %s -mtriple=avr | FileCheck %s
+; RUN: llc -mcpu=at90usb82 < %s -mtriple=avr | FileCheck %s
; Tests lowering of multiplication to compiler support routines.
diff --git a/llvm/test/CodeGen/AVR/std-immediate-overflow.ll b/llvm/test/CodeGen/AVR/std-immediate-overflow.ll
index 18ccb79d3a5f89..938c5a6c446516 100644
--- a/llvm/test/CodeGen/AVR/std-immediate-overflow.ll
+++ b/llvm/test/CodeGen/AVR/std-immediate-overflow.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=avr -filetype=asm -O1 < %s | FileCheck %s
+; RUN: llc -mtriple=avr -filetype=asm -O1 < %s | FileCheck %s
define void @check60(ptr %1) {
; CHECK-LABEL: check60:
diff --git a/llvm/test/CodeGen/AVR/std-ldd-immediate-overflow.ll b/llvm/test/CodeGen/AVR/std-ldd-immediate-overflow.ll
index 9f6fd5521f643f..31b93cfa0e4fb7 100644
--- a/llvm/test/CodeGen/AVR/std-ldd-immediate-overflow.ll
+++ b/llvm/test/CodeGen/AVR/std-ldd-immediate-overflow.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 < %s -march=avr | FileCheck %s
+; RUN: llc -O0 < %s -mtriple=avr | FileCheck %s
define i32 @std_ldd_overflow() {
%src = alloca [4 x i8]
diff --git a/llvm/test/CodeGen/AVR/stdwstk.ll b/llvm/test/CodeGen/AVR/stdwstk.ll
index 51e5c115f16a3e..8cafa751e6adf5 100644
--- a/llvm/test/CodeGen/AVR/stdwstk.ll
+++ b/llvm/test/CodeGen/AVR/stdwstk.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr -mcpu=atmega328 -O1 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=avr -mcpu=atmega328 -O1 -verify-machineinstrs | FileCheck %s
; CHECK-NOT: stdwstk
; Checks that we expand STDWSPQRr always - even if it appears outside of the
diff --git a/llvm/test/CodeGen/AVR/store-undef.ll b/llvm/test/CodeGen/AVR/store-undef.ll
index 63d938a5e58894..a7a4e8c794f4bd 100644
--- a/llvm/test/CodeGen/AVR/store-undef.ll
+++ b/llvm/test/CodeGen/AVR/store-undef.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
; This test checks that we can successfully lower a store
; to an undefined pointer.
diff --git a/llvm/test/CodeGen/AVR/store.ll b/llvm/test/CodeGen/AVR/store.ll
index 4af4e0449643a8..aab02709de7a6a 100644
--- a/llvm/test/CodeGen/AVR/store.ll
+++ b/llvm/test/CodeGen/AVR/store.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6,sram < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6,sram < %s -mtriple=avr | FileCheck %s
define void @store8(ptr %x, i8 %y) {
; CHECK-LABEL: store8:
diff --git a/llvm/test/CodeGen/AVR/sub.ll b/llvm/test/CodeGen/AVR/sub.ll
index 7a65a6004974e8..5171bcbe1ccf91 100644
--- a/llvm/test/CodeGen/AVR/sub.ll
+++ b/llvm/test/CodeGen/AVR/sub.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
define i8 @sub8_reg_reg(i8 %a, i8 %b) {
; CHECK-LABEL: sub8_reg_reg:
diff --git a/llvm/test/CodeGen/AVR/trunc.ll b/llvm/test/CodeGen/AVR/trunc.ll
index 30b530b1df90fd..bc98494df9b94d 100644
--- a/llvm/test/CodeGen/AVR/trunc.ll
+++ b/llvm/test/CodeGen/AVR/trunc.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
define i8 @trunc8_loreg(i16 %x, i16 %y) {
; CHECK-LABEL: trunc8_loreg:
diff --git a/llvm/test/CodeGen/AVR/umul-with-overflow.ll b/llvm/test/CodeGen/AVR/umul-with-overflow.ll
index 6df07381515437..ab323b0a621767 100644
--- a/llvm/test/CodeGen/AVR/umul-with-overflow.ll
+++ b/llvm/test/CodeGen/AVR/umul-with-overflow.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6 < %s -mtriple=avr | FileCheck %s
define i1 @unsigned_multiplication_did_overflow(i8, i8) unnamed_addr {
; CHECK-LABEL: unsigned_multiplication_did_overflow:
diff --git a/llvm/test/CodeGen/AVR/umul.with.overflow.i16-bug.ll b/llvm/test/CodeGen/AVR/umul.with.overflow.i16-bug.ll
index 9ccb5d04aa0757..5b8a5beadcb226 100644
--- a/llvm/test/CodeGen/AVR/umul.with.overflow.i16-bug.ll
+++ b/llvm/test/CodeGen/AVR/umul.with.overflow.i16-bug.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O1 < %s -march=avr | FileCheck %s
+; RUN: llc -O1 < %s -mtriple=avr | FileCheck %s
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.9"
diff --git a/llvm/test/CodeGen/AVR/unaligned-atomic-ops.ll b/llvm/test/CodeGen/AVR/unaligned-atomic-ops.ll
index 4c8a5d38ef878d..27359b6263ad88 100644
--- a/llvm/test/CodeGen/AVR/unaligned-atomic-ops.ll
+++ b/llvm/test/CodeGen/AVR/unaligned-atomic-ops.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=addsubiw < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=addsubiw < %s -mtriple=avr | FileCheck %s
; This verifies that the backend can handle an unaligned atomic load and store.
;
diff --git a/llvm/test/CodeGen/AVR/varargs.ll b/llvm/test/CodeGen/AVR/varargs.ll
index 2ea670c534da00..df44374734969e 100644
--- a/llvm/test/CodeGen/AVR/varargs.ll
+++ b/llvm/test/CodeGen/AVR/varargs.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=sram,movw,addsubiw < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=sram,movw,addsubiw < %s -mtriple=avr | FileCheck %s
declare void @llvm.va_start(ptr)
declare i16 @vsprintf(ptr nocapture, ptr nocapture, ptr)
diff --git a/llvm/test/CodeGen/AVR/xor.ll b/llvm/test/CodeGen/AVR/xor.ll
index 3f04feb9e2ae8f..4ac06ca626c071 100644
--- a/llvm/test/CodeGen/AVR/xor.ll
+++ b/llvm/test/CodeGen/AVR/xor.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
define i8 @xor8_reg_reg(i8 %a, i8 %b) {
; CHECK-LABEL: xor8_reg_reg:
diff --git a/llvm/test/CodeGen/AVR/zeroreg.ll b/llvm/test/CodeGen/AVR/zeroreg.ll
index 6187b6b97380b9..132d03793928d5 100644
--- a/llvm/test/CodeGen/AVR/zeroreg.ll
+++ b/llvm/test/CodeGen/AVR/zeroreg.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6,sram < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6,sram < %s -mtriple=avr | FileCheck %s
; This file tests whether the compiler correctly works with the r1 register,
; clearing it when needed.
diff --git a/llvm/test/CodeGen/AVR/zext.ll b/llvm/test/CodeGen/AVR/zext.ll
index c95ad03053c76e..e49b9036df6306 100644
--- a/llvm/test/CodeGen/AVR/zext.ll
+++ b/llvm/test/CodeGen/AVR/zext.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr | FileCheck %s
; zext R25:R24, R24
; eor R25, R25
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