[llvm] 5240e0b - [VE,test] Change llc -march= to -mtriple=
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Sun Dec 15 10:24:19 PST 2024
Author: Fangrui Song
Date: 2024-12-15T10:24:14-08:00
New Revision: 5240e0b891fc4bf69d362199f70c94c28a7b9465
URL: https://github.com/llvm/llvm-project/commit/5240e0b891fc4bf69d362199f70c94c28a7b9465
DIFF: https://github.com/llvm/llvm-project/commit/5240e0b891fc4bf69d362199f70c94c28a7b9465.diff
LOG: [VE,test] Change llc -march= to -mtriple=
Similar to 806761a7629df268c8aed49657aeccffa6bca449
-mtriple= specifies the full target triple while -march= merely sets the
architecture part of the default target triple, leaving a target triple which
may not make sense.
Therefore, -march= is error-prone and not recommended for tests without a target
triple. The issue has been benign as we recognize $ve-apple-darwin as ELF instead
of rejecting it outrightly.
Added:
Modified:
llvm/test/CodeGen/VE/Packed/vec_fneg.ll
llvm/test/CodeGen/VE/Packed/vp_add.ll
llvm/test/CodeGen/VE/Packed/vp_and.ll
llvm/test/CodeGen/VE/Packed/vp_fadd.ll
llvm/test/CodeGen/VE/Packed/vp_fdiv.ll
llvm/test/CodeGen/VE/Packed/vp_fmul.ll
llvm/test/CodeGen/VE/Packed/vp_fsub.ll
llvm/test/CodeGen/VE/Packed/vp_mul.ll
llvm/test/CodeGen/VE/Packed/vp_or.ll
llvm/test/CodeGen/VE/Packed/vp_sdiv.ll
llvm/test/CodeGen/VE/Packed/vp_shl.ll
llvm/test/CodeGen/VE/Packed/vp_sra.ll
llvm/test/CodeGen/VE/Packed/vp_srl.ll
llvm/test/CodeGen/VE/Packed/vp_sub.ll
llvm/test/CodeGen/VE/Packed/vp_udiv.ll
llvm/test/CodeGen/VE/Packed/vp_xor.ll
llvm/test/CodeGen/VE/Vector/expand_single_elem_build_vec.ll
llvm/test/CodeGen/VE/Vector/feature_vpu.ll
llvm/test/CodeGen/VE/Vector/vec_fma.ll
llvm/test/CodeGen/VE/Vector/vec_fneg.ll
llvm/test/CodeGen/VE/Vector/vec_reduce_add.ll
llvm/test/CodeGen/VE/Vector/vec_reduce_and.ll
llvm/test/CodeGen/VE/Vector/vec_reduce_or.ll
llvm/test/CodeGen/VE/Vector/vec_reduce_smax.ll
llvm/test/CodeGen/VE/Vector/vec_reduce_xor.ll
llvm/test/CodeGen/VE/Vector/vec_select.ll
llvm/test/CodeGen/VE/Vector/vp_add.ll
llvm/test/CodeGen/VE/Vector/vp_and.ll
llvm/test/CodeGen/VE/Vector/vp_ashr.ll
llvm/test/CodeGen/VE/Vector/vp_fadd.ll
llvm/test/CodeGen/VE/Vector/vp_fadd_merge.ll
llvm/test/CodeGen/VE/Vector/vp_fdiv.ll
llvm/test/CodeGen/VE/Vector/vp_fdiv_merge.ll
llvm/test/CodeGen/VE/Vector/vp_fma.ll
llvm/test/CodeGen/VE/Vector/vp_fma_merge.ll
llvm/test/CodeGen/VE/Vector/vp_fmul.ll
llvm/test/CodeGen/VE/Vector/vp_fmul_merge.ll
llvm/test/CodeGen/VE/Vector/vp_fsub.ll
llvm/test/CodeGen/VE/Vector/vp_fsub_merge.ll
llvm/test/CodeGen/VE/Vector/vp_lshr.ll
llvm/test/CodeGen/VE/Vector/vp_merge.ll
llvm/test/CodeGen/VE/Vector/vp_mul.ll
llvm/test/CodeGen/VE/Vector/vp_or.ll
llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll
llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll
llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll
llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll
llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll
llvm/test/CodeGen/VE/Vector/vp_sdiv.ll
llvm/test/CodeGen/VE/Vector/vp_select.ll
llvm/test/CodeGen/VE/Vector/vp_shl.ll
llvm/test/CodeGen/VE/Vector/vp_sra.ll
llvm/test/CodeGen/VE/Vector/vp_srem.ll
llvm/test/CodeGen/VE/Vector/vp_srl.ll
llvm/test/CodeGen/VE/Vector/vp_sub.ll
llvm/test/CodeGen/VE/Vector/vp_udiv.ll
llvm/test/CodeGen/VE/Vector/vp_urem.ll
llvm/test/CodeGen/VE/Vector/vp_xor.ll
llvm/test/CodeGen/VE/null-mctargetstreamer.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/VE/Packed/vec_fneg.ll b/llvm/test/CodeGen/VE/Packed/vec_fneg.ll
index 5209398a7dec50..6c2989cbf1117f 100644
--- a/llvm/test/CodeGen/VE/Packed/vec_fneg.ll
+++ b/llvm/test/CodeGen/VE/Packed/vec_fneg.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
define fastcc <512 x float> @test_vec_fneg_v512f32_v(<512 x float> %v) {
; CHECK-LABEL: test_vec_fneg_v512f32_v:
diff --git a/llvm/test/CodeGen/VE/Packed/vp_add.ll b/llvm/test/CodeGen/VE/Packed/vp_add.ll
index 7942cf45cf44cc..3e64d6fe9b1dbc 100644
--- a/llvm/test/CodeGen/VE/Packed/vp_add.ll
+++ b/llvm/test/CodeGen/VE/Packed/vp_add.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <512 x i32> @llvm.vp.add.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Packed/vp_and.ll b/llvm/test/CodeGen/VE/Packed/vp_and.ll
index 8f47837c71e930..2c9aa57001e081 100644
--- a/llvm/test/CodeGen/VE/Packed/vp_and.ll
+++ b/llvm/test/CodeGen/VE/Packed/vp_and.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <512 x i32> @llvm.vp.and.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Packed/vp_fadd.ll b/llvm/test/CodeGen/VE/Packed/vp_fadd.ll
index e99c7c47060a8a..be201ed461a982 100644
--- a/llvm/test/CodeGen/VE/Packed/vp_fadd.ll
+++ b/llvm/test/CodeGen/VE/Packed/vp_fadd.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <512 x float> @llvm.vp.fadd.v512f32(<512 x float>, <512 x float>, <512 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Packed/vp_fdiv.ll b/llvm/test/CodeGen/VE/Packed/vp_fdiv.ll
index 50c3fa189ea857..dac6fc7296d286 100644
--- a/llvm/test/CodeGen/VE/Packed/vp_fdiv.ll
+++ b/llvm/test/CodeGen/VE/Packed/vp_fdiv.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <512 x float> @llvm.vp.fdiv.v512f32(<512 x float>, <512 x float>, <512 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Packed/vp_fmul.ll b/llvm/test/CodeGen/VE/Packed/vp_fmul.ll
index 6de32a3127c826..853b0ee9a84e9f 100644
--- a/llvm/test/CodeGen/VE/Packed/vp_fmul.ll
+++ b/llvm/test/CodeGen/VE/Packed/vp_fmul.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <512 x float> @llvm.vp.fmul.v512f32(<512 x float>, <512 x float>, <512 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Packed/vp_fsub.ll b/llvm/test/CodeGen/VE/Packed/vp_fsub.ll
index 8c2e19c68543b2..e5fd8bd7456c6d 100644
--- a/llvm/test/CodeGen/VE/Packed/vp_fsub.ll
+++ b/llvm/test/CodeGen/VE/Packed/vp_fsub.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <512 x float> @llvm.vp.fsub.v512f32(<512 x float>, <512 x float>, <512 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Packed/vp_mul.ll b/llvm/test/CodeGen/VE/Packed/vp_mul.ll
index 26271eef99454f..e5ee8ba6be5912 100644
--- a/llvm/test/CodeGen/VE/Packed/vp_mul.ll
+++ b/llvm/test/CodeGen/VE/Packed/vp_mul.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <512 x i32> @llvm.vp.mul.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Packed/vp_or.ll b/llvm/test/CodeGen/VE/Packed/vp_or.ll
index 186b70f772d2fa..db46aa2d86e548 100644
--- a/llvm/test/CodeGen/VE/Packed/vp_or.ll
+++ b/llvm/test/CodeGen/VE/Packed/vp_or.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <512 x i32> @llvm.vp.or.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Packed/vp_sdiv.ll b/llvm/test/CodeGen/VE/Packed/vp_sdiv.ll
index 24202eaecedb78..45359f213ab42c 100644
--- a/llvm/test/CodeGen/VE/Packed/vp_sdiv.ll
+++ b/llvm/test/CodeGen/VE/Packed/vp_sdiv.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <512 x i32> @llvm.vp.sdiv.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Packed/vp_shl.ll b/llvm/test/CodeGen/VE/Packed/vp_shl.ll
index 3e11d4bdcc655f..3697c6ec92b380 100644
--- a/llvm/test/CodeGen/VE/Packed/vp_shl.ll
+++ b/llvm/test/CodeGen/VE/Packed/vp_shl.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <512 x i32> @llvm.vp.shl.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Packed/vp_sra.ll b/llvm/test/CodeGen/VE/Packed/vp_sra.ll
index 1b58a2f89c6efd..3fe690c97d6002 100644
--- a/llvm/test/CodeGen/VE/Packed/vp_sra.ll
+++ b/llvm/test/CodeGen/VE/Packed/vp_sra.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <512 x i32> @llvm.vp.ashr.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Packed/vp_srl.ll b/llvm/test/CodeGen/VE/Packed/vp_srl.ll
index 116b506a8db99a..f835549afc9c9e 100644
--- a/llvm/test/CodeGen/VE/Packed/vp_srl.ll
+++ b/llvm/test/CodeGen/VE/Packed/vp_srl.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <512 x i32> @llvm.vp.lshr.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Packed/vp_sub.ll b/llvm/test/CodeGen/VE/Packed/vp_sub.ll
index e846af91af031b..8ebf8ef8b3c26e 100644
--- a/llvm/test/CodeGen/VE/Packed/vp_sub.ll
+++ b/llvm/test/CodeGen/VE/Packed/vp_sub.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <512 x i32> @llvm.vp.sub.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Packed/vp_udiv.ll b/llvm/test/CodeGen/VE/Packed/vp_udiv.ll
index 80e1729bf64a09..fa19f1438f746e 100644
--- a/llvm/test/CodeGen/VE/Packed/vp_udiv.ll
+++ b/llvm/test/CodeGen/VE/Packed/vp_udiv.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <512 x i32> @llvm.vp.udiv.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Packed/vp_xor.ll b/llvm/test/CodeGen/VE/Packed/vp_xor.ll
index b7f1a3423d45dc..51b1b7f5bfa7a2 100644
--- a/llvm/test/CodeGen/VE/Packed/vp_xor.ll
+++ b/llvm/test/CodeGen/VE/Packed/vp_xor.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <512 x i32> @llvm.vp.xor.v512i32(<512 x i32>, <512 x i32>, <512 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/expand_single_elem_build_vec.ll b/llvm/test/CodeGen/VE/Vector/expand_single_elem_build_vec.ll
index 42c45531924603..f9536483b98a48 100644
--- a/llvm/test/CodeGen/VE/Vector/expand_single_elem_build_vec.ll
+++ b/llvm/test/CodeGen/VE/Vector/expand_single_elem_build_vec.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
; Function Attrs: norecurse nounwind readnone
; Check that a single-element insertion is lowered to a insert_vector_elt node for isel.
diff --git a/llvm/test/CodeGen/VE/Vector/feature_vpu.ll b/llvm/test/CodeGen/VE/Vector/feature_vpu.ll
index c64df511010234..0c49d54f65c934 100644
--- a/llvm/test/CodeGen/VE/Vector/feature_vpu.ll
+++ b/llvm/test/CodeGen/VE/Vector/feature_vpu.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=ve -mattr=help 2>&1 > /dev/null | FileCheck %s
+; RUN: llc -mtriple=ve -mattr=help 2>&1 > /dev/null | FileCheck %s
; CHECK: Available features for this target:
; CHECK: vpu - Enable the VPU.
diff --git a/llvm/test/CodeGen/VE/Vector/vec_fma.ll b/llvm/test/CodeGen/VE/Vector/vec_fma.ll
index e0a92f165d99fb..0e77436d6651b9 100644
--- a/llvm/test/CodeGen/VE/Vector/vec_fma.ll
+++ b/llvm/test/CodeGen/VE/Vector/vec_fma.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x float> @llvm.fma.v256f32(<256 x float>, <256 x float>, <256 x float>)
diff --git a/llvm/test/CodeGen/VE/Vector/vec_fneg.ll b/llvm/test/CodeGen/VE/Vector/vec_fneg.ll
index db1cafccb67553..efa17a9c1f38e9 100644
--- a/llvm/test/CodeGen/VE/Vector/vec_fneg.ll
+++ b/llvm/test/CodeGen/VE/Vector/vec_fneg.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
define fastcc <256 x float> @test_vec_fneg_v256f32_v(<256 x float> %v) {
; CHECK-LABEL: test_vec_fneg_v256f32_v:
diff --git a/llvm/test/CodeGen/VE/Vector/vec_reduce_add.ll b/llvm/test/CodeGen/VE/Vector/vec_reduce_add.ll
index 3648850697fbc6..ee0191752c8abe 100644
--- a/llvm/test/CodeGen/VE/Vector/vec_reduce_add.ll
+++ b/llvm/test/CodeGen/VE/Vector/vec_reduce_add.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -O0 --mtriple=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vector.reduce.add.v256i64(<256 x i64>)
diff --git a/llvm/test/CodeGen/VE/Vector/vec_reduce_and.ll b/llvm/test/CodeGen/VE/Vector/vec_reduce_and.ll
index 53af0f9c403425..04a2b26ef61728 100644
--- a/llvm/test/CodeGen/VE/Vector/vec_reduce_and.ll
+++ b/llvm/test/CodeGen/VE/Vector/vec_reduce_and.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -O0 --mtriple=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vector.reduce.and.v256i64(<256 x i64>)
diff --git a/llvm/test/CodeGen/VE/Vector/vec_reduce_or.ll b/llvm/test/CodeGen/VE/Vector/vec_reduce_or.ll
index f30b77449b04df..8e85eb8c29d36d 100644
--- a/llvm/test/CodeGen/VE/Vector/vec_reduce_or.ll
+++ b/llvm/test/CodeGen/VE/Vector/vec_reduce_or.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -O0 --mtriple=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vector.reduce.or.v256i64(<256 x i64>)
diff --git a/llvm/test/CodeGen/VE/Vector/vec_reduce_smax.ll b/llvm/test/CodeGen/VE/Vector/vec_reduce_smax.ll
index 822b541e0b0471..f52dd65f3f9a70 100644
--- a/llvm/test/CodeGen/VE/Vector/vec_reduce_smax.ll
+++ b/llvm/test/CodeGen/VE/Vector/vec_reduce_smax.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -O0 --mtriple=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vector.reduce.smax.v256i64(<256 x i64>)
diff --git a/llvm/test/CodeGen/VE/Vector/vec_reduce_xor.ll b/llvm/test/CodeGen/VE/Vector/vec_reduce_xor.ll
index 47b291f3ecab6f..f7542f749b916c 100644
--- a/llvm/test/CodeGen/VE/Vector/vec_reduce_xor.ll
+++ b/llvm/test/CodeGen/VE/Vector/vec_reduce_xor.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -O0 --mtriple=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vector.reduce.xor.v256i64(<256 x i64>)
diff --git a/llvm/test/CodeGen/VE/Vector/vec_select.ll b/llvm/test/CodeGen/VE/Vector/vec_select.ll
index 8ccbff7828d3f5..5c358338a9ea7b 100644
--- a/llvm/test/CodeGen/VE/Vector/vec_select.ll
+++ b/llvm/test/CodeGen/VE/Vector/vec_select.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x i32> @llvm.vec.select.v256i32(<256 x i1>, <256 x i32>, <256 x i32>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_add.ll b/llvm/test/CodeGen/VE/Vector/vp_add.ll
index 8d69bd4c728c83..bd6f25bdacbca4 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_add.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_add.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x i32> @llvm.vp.add.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_and.ll b/llvm/test/CodeGen/VE/Vector/vp_and.ll
index 084212c66fb499..b28c4865278254 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_and.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_and.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x i32> @llvm.vp.and.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_ashr.ll b/llvm/test/CodeGen/VE/Vector/vp_ashr.ll
index ef82ed5c9d19b7..fe7ad8d1b5a968 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_ashr.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_ashr.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x i32> @llvm.vp.ashr.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_fadd.ll b/llvm/test/CodeGen/VE/Vector/vp_fadd.ll
index 804235f4ea2643..9de2b26074e0ed 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_fadd.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_fadd.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x float> @llvm.vp.fadd.v256f32(<256 x float>, <256 x float>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_fadd_merge.ll b/llvm/test/CodeGen/VE/Vector/vp_fadd_merge.ll
index 742bc78c43e16c..9e340e1e105477 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_fadd_merge.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_fadd_merge.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x float> @llvm.vp.merge.v256f32(<256 x i1>, <256 x float>, <256 x float>, i32)
declare <256 x float> @llvm.vp.fadd.v256f32(<256 x float>, <256 x float>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_fdiv.ll b/llvm/test/CodeGen/VE/Vector/vp_fdiv.ll
index 669e1f9c9307a7..40e065a5fe59eb 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_fdiv.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_fdiv.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x float> @llvm.vp.fdiv.v256f32(<256 x float>, <256 x float>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_fdiv_merge.ll b/llvm/test/CodeGen/VE/Vector/vp_fdiv_merge.ll
index 0e9a428f518bb5..e0ffbfab4d0aea 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_fdiv_merge.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_fdiv_merge.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x float> @llvm.vp.merge.v256f32(<256 x i1>, <256 x float>, <256 x float>, i32)
declare <256 x float> @llvm.vp.fdiv.v256f32(<256 x float>, <256 x float>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_fma.ll b/llvm/test/CodeGen/VE/Vector/vp_fma.ll
index 69341844276380..cb61cb0236a3d3 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_fma.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_fma.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x float> @llvm.vp.fma.v256f32(<256 x float>, <256 x float>, <256 x float>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_fma_merge.ll b/llvm/test/CodeGen/VE/Vector/vp_fma_merge.ll
index da2851538c6596..825e475089e759 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_fma_merge.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_fma_merge.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x float> @llvm.vp.merge.v256f32(<256 x i1>, <256 x float>, <256 x float>, i32)
declare <256 x float> @llvm.vp.fma.v256f32(<256 x float>, <256 x float>, <256 x float>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_fmul.ll b/llvm/test/CodeGen/VE/Vector/vp_fmul.ll
index 0277e755f32cab..739573e0b3e393 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_fmul.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_fmul.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x float> @llvm.vp.fmul.v256f32(<256 x float>, <256 x float>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_fmul_merge.ll b/llvm/test/CodeGen/VE/Vector/vp_fmul_merge.ll
index c09fc01ce5e76e..3f00e621c22502 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_fmul_merge.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_fmul_merge.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x float> @llvm.vp.merge.v256f32(<256 x i1>, <256 x float>, <256 x float>, i32)
declare <256 x float> @llvm.vp.fmul.v256f32(<256 x float>, <256 x float>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_fsub.ll b/llvm/test/CodeGen/VE/Vector/vp_fsub.ll
index 8f51522ee681be..dcfc499cbd67cf 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_fsub.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_fsub.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x float> @llvm.vp.fsub.v256f32(<256 x float>, <256 x float>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_fsub_merge.ll b/llvm/test/CodeGen/VE/Vector/vp_fsub_merge.ll
index 2f10f6e7028ad1..e3f5e33544fb66 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_fsub_merge.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_fsub_merge.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x float> @llvm.vp.merge.v256f32(<256 x i1>, <256 x float>, <256 x float>, i32)
declare <256 x float> @llvm.vp.fsub.v256f32(<256 x float>, <256 x float>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_lshr.ll b/llvm/test/CodeGen/VE/Vector/vp_lshr.ll
index f071c88448900b..4ea6c76e866c46 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_lshr.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_lshr.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x i32> @llvm.vp.lshr.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_merge.ll b/llvm/test/CodeGen/VE/Vector/vp_merge.ll
index fdd38099b5b915..8b752aa9753a4a 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_merge.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_merge.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x i32> @llvm.vp.merge.v256i32(<256 x i1>, <256 x i32>, <256 x i32>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_mul.ll b/llvm/test/CodeGen/VE/Vector/vp_mul.ll
index f729200449ccd6..631f676a668de5 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_mul.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_mul.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x i32> @llvm.vp.mul.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_or.ll b/llvm/test/CodeGen/VE/Vector/vp_or.ll
index d3b5f324d64cbb..1ae6eb5c0a3ad4 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_or.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_or.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x i32> @llvm.vp.or.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll b/llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll
index 9e54053e9dd634..b76729d062f1ea 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -O0 --mtriple=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vp.reduce.add.v256i64(i64, <256 x i64>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll b/llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll
index af2868a0c438a6..fef21c5294a809 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -O0 --mtriple=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vp.reduce.and.v256i64(i64, <256 x i64>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll b/llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll
index 85f02a37a354f7..aa47e812693f73 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -O0 --mtriple=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vp.reduce.or.v256i64(i64, <256 x i64>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll b/llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll
index 766dd723dc9f11..59bdb210a0e54c 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -O0 --mtriple=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vp.reduce.smax.v256i64(i64, <256 x i64>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll b/llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll
index ac2de57b6baca9..9da1eb8db93252 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -O0 --march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -O0 --mtriple=ve -mattr=+vpu | FileCheck %s
declare i64 @llvm.vp.reduce.xor.v256i64(i64, <256 x i64>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_sdiv.ll b/llvm/test/CodeGen/VE/Vector/vp_sdiv.ll
index fa2d435cff4d07..24d62f5e8a82d6 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_sdiv.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_sdiv.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x i32> @llvm.vp.sdiv.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_select.ll b/llvm/test/CodeGen/VE/Vector/vp_select.ll
index f716efa471942a..3858af7ad50170 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_select.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_select.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x i32> @llvm.vp.select.v256i32(<256 x i1>, <256 x i32>, <256 x i32>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_shl.ll b/llvm/test/CodeGen/VE/Vector/vp_shl.ll
index 94a4af3eb4c2d6..5929e00bcb158b 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_shl.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_shl.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x i32> @llvm.vp.shl.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_sra.ll b/llvm/test/CodeGen/VE/Vector/vp_sra.ll
index 3cdb424dc27e9f..a45d694e5334db 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_sra.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_sra.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x i32> @llvm.vp.ashr.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_srem.ll b/llvm/test/CodeGen/VE/Vector/vp_srem.ll
index ffd93e340ebdc9..4895b9cb699aeb 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_srem.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_srem.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x i32> @llvm.vp.srem.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_srl.ll b/llvm/test/CodeGen/VE/Vector/vp_srl.ll
index c41aa1928213cc..f00688d8a2bf9b 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_srl.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_srl.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x i32> @llvm.vp.lshr.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_sub.ll b/llvm/test/CodeGen/VE/Vector/vp_sub.ll
index 5c1cd291a3415d..b0f4726c23ebbc 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_sub.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_sub.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x i32> @llvm.vp.sub.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_udiv.ll b/llvm/test/CodeGen/VE/Vector/vp_udiv.ll
index c0139a7f2b77b0..7af64053149089 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_udiv.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_udiv.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x i32> @llvm.vp.udiv.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_urem.ll b/llvm/test/CodeGen/VE/Vector/vp_urem.ll
index 0620c89781443e..fc19f53abdfaa4 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_urem.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_urem.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x i32> @llvm.vp.urem.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/Vector/vp_xor.ll b/llvm/test/CodeGen/VE/Vector/vp_xor.ll
index a7e640ce1cfd3c..ae6b0f80333093 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_xor.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_xor.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
declare <256 x i32> @llvm.vp.xor.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
diff --git a/llvm/test/CodeGen/VE/null-mctargetstreamer.ll b/llvm/test/CodeGen/VE/null-mctargetstreamer.ll
index fd0ded414391c2..9ec40e37053915 100644
--- a/llvm/test/CodeGen/VE/null-mctargetstreamer.ll
+++ b/llvm/test/CodeGen/VE/null-mctargetstreamer.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=ve -filetype=null %s
+; RUN: llc -mtriple=ve -filetype=null %s
define void @foo() {
ret void
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