[llvm] [GlobalISel][AArch64] Legalize G_FABS and G_FNEG for SVE (PR #114784)

[Thorsten Schütt via llvm-commits]

tschuett wrote:

> > Fixed vectors. In the patterns above there is `PTRUE_D 31` on the predicate register, where `31` means `ALL`. All vector lanes are active. For fixed vectors, the dag uses ptrue with less active lanes. Selection might work in C++ by using ptrue with less active lanes. For the moment, I have no idea how to do that with patterns.
> 
> Why does it need to be done with patterns? Why can't we write C++ for GISel? AArch64 has a 8000 lines of C++ in AArch64InstructionSelector.cpp a lot of it to do custom selection. There's also the AArch64PostLegalizerLowering.cpp pass that puts things in a form for isel.

I bet the fixed length vectors are intrinsics. Either they are selected automatic already or we have to do the work in C++ in the selector.

https://github.com/llvm/llvm-project/pull/114784