[llvm] [RISCV][VLOPT] Add vector mask producing integer instructions to isSupportedInstr and getOperandInfo (PR #119733)

[Michael Maitland via llvm-commits]

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@@ -438,7 +444,11 @@ static OperandInfo getOperandInfo(const MachineInstr &MI,
   case RISCV::VWMACC_VX:
   case RISCV::VWMACCSU_VV:
   case RISCV::VWMACCSU_VX:
-  case RISCV::VWMACCUS_VX: {
+  case RISCV::VWMACCUS_VX:
+  // Vector Single-Width Fractional Multiply with Rounding and Saturation
+  // Destination EEW=2*SEW and EMUL=2*EMUL. Source EEW=SEW and EMUL=LMUL.
+  case RISCV::VSMUL_VV:
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michaelmaitland wrote:

Sorry, this wasn't supposed to be a part of this patch anyway. Thanks for the info though.

https://github.com/llvm/llvm-project/pull/119733