[llvm] [RISCV][VLOPT] Add getOperandInfo for Vector Store Whole Register Instructions (PR #119570)

[Craig Topper via llvm-commits]

================
@@ -247,6 +247,25 @@ static OperandInfo getOperandInfo(const MachineInstr &MI,
     llvm_unreachable("Configuration setting instructions do not read or write "
                      "vector registers");
 
+  // Vector Store Whole Register Instructions
+  // EMUL=nr. EEW=eew. Since in-register byte layouts are idential to in-memory
+  // byte layouts, the same data is writen to destination register regardless
+  // of EEW. eew is just a hint to the hardware and has not functional impact.
+  // Therefore, it is be okay if we ignore eew and always use the same EEW to
+  // create more optimization opportunities.
+  // FIXME: Instead of using any SEW, we really should return the SEW in the
+  // instruction and add a field to OperandInfo that says the SEW is just a hint
+  // so that this optimization can use any sew to construct a ratio.
+  case RISCV::VS1R_V:
----------------
topperc wrote:

These instructions don't have an SEW or VL operand so I think we would fail this check before we get here

```
    const MCInstrDesc &Desc = UserMI.getDesc();                                  
    if (!RISCVII::hasVLOp(Desc.TSFlags) || !RISCVII::hasSEWOp(Desc.TSFlags)) {   
      LLVM_DEBUG(dbgs() << "    Abort due to lack of VL or SEW, assume that"     
                           " use VLMAX\n");                                      
      CanReduceVL = false;                                                       
      break;                                                                     
    } 
```

https://github.com/llvm/llvm-project/pull/119570