[llvm] [RISCV][VLOPT] Add getOperandInfo for Vector Store Whole Register Instructions (PR #119570)

[Craig Topper via llvm-commits]

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@@ -247,6 +247,25 @@ static OperandInfo getOperandInfo(const MachineInstr &MI,
     llvm_unreachable("Configuration setting instructions do not read or write "
                      "vector registers");
 
+  // Vector Store Whole Register Instructions
+  // EMUL=nr. EEW=eew. Since in-register byte layouts are idential to in-memory
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topperc wrote:

idential -> identical

https://github.com/llvm/llvm-project/pull/119570