[llvm] [AMDGPU][True16][CodeGen] build_vector pattern in true16 (PR #118904)

[Joe Nash via llvm-commits]

================
@@ -3275,6 +3275,8 @@ def : GCNPat <
   (COPY_TO_REGCLASS SReg_32:$src0, SReg_32)
 >;
 
+foreach p = [NotHasTrue16BitInsts, UseFakeTrue16Insts] in
----------------
Sisyph wrote:

In some cases the treatment for NotHasTrue16BitInsts and UseFakeTrue16Insts is the same. Like here, for ISel patterns. In some cases the treatment is different, like for defining Fake16 instructions that can only use the lo128 VGPRs. Also, we plan to remove Fake16 instructions and patterns when the targets they are used on are switched over to real16. So it doesn't seem worth it to define a new predicate to me, we could not remove any existing predicate. 

https://github.com/llvm/llvm-project/pull/118904