[llvm] [AArch64][SVE] Add partial reduction SDNodes (PR #117185)

[James Chesterman via llvm-commits]

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@@ -21834,15 +21824,23 @@ SDValue tryLowerPartialReductionToWideAdd(SDNode *N,
   auto Acc = N->getOperand(0);
   auto Input = N->getOperand(1);
 
-  EVT AccVT = Acc.getValueType();
+  unsigned Opcode = N->getOpcode();
+  unsigned InputOpcode = Input.getOpcode();
+  if (ISD::isExtOpcode(InputOpcode)) {
+    Input = Input.getOperand(0);
+    if (InputOpcode == ISD::SIGN_EXTEND)
+      Opcode = ISD::PARTIAL_REDUCE_SADD;
+  }
+
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JamesChesterman wrote:

Currently there would be no node for `ISD::PARTIAL_REDUCE_SADD` made anymore. But with the legalisation, I would make it output a node with the opcode `ISD::PARTIAL_REDUCE_SADD` here. This would then go through legalisation and the execution would then lead back to `tryLowerPartialReductionToWideAdd`. 
I originally left this out of this patch because it wasn't necessary to get it to work. But I will go back and make it return the node, just to make sure it all works properly.

https://github.com/llvm/llvm-project/pull/117185