[llvm] [AArch64][SVE] Add partial reduction SDNodes (PR #117185)

[Benjamin Maxwell via llvm-commits]

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@@ -21834,15 +21824,23 @@ SDValue tryLowerPartialReductionToWideAdd(SDNode *N,
   auto Acc = N->getOperand(0);
   auto Input = N->getOperand(1);
 
-  EVT AccVT = Acc.getValueType();
+  unsigned Opcode = N->getOpcode();
+  unsigned InputOpcode = Input.getOpcode();
+  if (ISD::isExtOpcode(InputOpcode)) {
+    Input = Input.getOperand(0);
+    if (InputOpcode == ISD::SIGN_EXTEND)
+      Opcode = ISD::PARTIAL_REDUCE_SADD;
+  }
+
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MacDue wrote:

Correct me if I'm wrong, but it looks like no node of `ISD::PARTIAL_REDUCE_SADD` is made anymore? 

I think what Paul meant was there would be dag-combine that goes from `ISD::PARTIAL_REDUCE_UADD` to `ISD::PARTIAL_REDUCE_SADD` (by checking the inputs). Then later where would be a lowering for `ISD::PARTIAL_REDUCE_UADD` and `ISD::PARTIAL_REDUCE_SADD`. 


https://github.com/llvm/llvm-project/pull/117185