[llvm] [AArch64][SVE] Add partial reduction SDNodes (PR #117185)

[Paul Walker via llvm-commits]

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@@ -1451,6 +1451,13 @@ enum NodeType {
   VECREDUCE_UMAX,
   VECREDUCE_UMIN,
 
+  // These correspond to the `llvm.experimental.vector.partial.reduce.add`
+  // intrinsic
+  // Operands: Accumulator, Input
+  // Outputs: Output
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paulwalker-arm wrote:

The semantics of these nodes do not fully align with the intrinsic they are associated with, so it would be better to document them in isolation.

https://github.com/llvm/llvm-project/pull/117185