[llvm] [AArch64][SVE] Add partial reduction SDNodes (PR #117185)

[Paul Walker via llvm-commits]

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@@ -1595,10 +1595,12 @@ class SelectionDAG {
   /// the target's desired shift amount type.
   SDValue getShiftAmountOperand(EVT LHSTy, SDValue Op);
 
-  /// Create the DAG equivalent of vector_partial_reduce where Op1 and Op2 are
-  /// its operands and ReducedTY is the intrinsic's return type.
-  SDValue getPartialReduceAdd(SDLoc DL, EVT ReducedTy, SDValue Op1,
-                              SDValue Op2);
+  /// Expands PARTIAL_REDUCE_S/UADD nodes to a sequence of subvector extracts
+  /// followed by vector adds.
+  /// \p Op1 Accumulator for where the result is stored for the partial
+  /// reduction operation.
+  /// \p Op2 Input for the partial reduction operation.
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paulwalker-arm wrote:

There's no need to go into details here because the output is an implementation details that might change because there's several way we could expand the operation..

https://github.com/llvm/llvm-project/pull/117185