[llvm] [AArch64][SVE] Add partial reduction SDNodes (PR #117185)

[Paul Walker via llvm-commits]

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@@ -8126,15 +8126,21 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
     return;
   }
   case Intrinsic::experimental_vector_partial_reduce_add: {
+    SDLoc dl = getCurSDLoc();
+    SDValue Acc = getValue(I.getOperand(0));
+    EVT AccVT = Acc.getValueType();
+    SDValue Input = getValue(I.getOperand(1));
 
     if (!TLI.shouldExpandPartialReductionIntrinsic(cast<IntrinsicInst>(&I))) {
-      visitTargetIntrinsic(I, Intrinsic);
+      if (TLI.isPartialReductionInputSigned(Input))
+        setValue(&I,
+                 DAG.getNode(ISD::PARTIAL_REDUCE_SADD, dl, AccVT, Acc, Input));
+      else
+        setValue(&I,
+                 DAG.getNode(ISD::PARTIAL_REDUCE_UADD, dl, AccVT, Acc, Input));
----------------
paulwalker-arm wrote:

The signedness is a property of the operation rather than a a property of its data.  This is why the partial.reduce.add intrinsic does not require signedness information because it requires all operands to be the same size and thus there is no implicit extension happening as part of the operation.

During initial selection the choice of `ISD::PARTIAL_REDUCE_SADD` to `ISD::PARTIAL_REDUCE_UADD` does not matter because it will also have all operands being the same size.  In such circumstances you should just pick one as the canonical form.

The choice of node only becomes important when a transformation changes the operation to take a second operand that has a smaller element size than the first.  This is because it is converting an explicit extension into an implicit one.  Doing this is most likely going to be the result of a DAG combine or perhaps legalisation depending on the circumstance.

https://github.com/llvm/llvm-project/pull/117185