[llvm] [AArch64][SVE] Add partial reduction SDNodes (PR #117185)

[Paul Walker via llvm-commits]

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@@ -21808,45 +21822,40 @@ SDValue tryLowerPartialReductionToDot(SDNode *N,
 SDValue tryLowerPartialReductionToWideAdd(SDNode *N,
                                           const AArch64Subtarget *Subtarget,
                                           SelectionDAG &DAG) {
-
-  assert(N->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
-         getIntrinsicID(N) ==
-             Intrinsic::experimental_vector_partial_reduce_add &&
-         "Expected a partial reduction node");
-
   if (!Subtarget->isSVEorStreamingSVEAvailable())
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paulwalker-arm wrote:

This existing code looks wrong to me because the wide add instructions are only available in SVE2 (or SME in streaming mode).  I'm pretty sure this code will lead to an internal compiler error when only SVE is available and is worth fixing asap as a new PR.

https://github.com/llvm/llvm-project/pull/117185