[llvm] [AArch64][SVE] Add partial reduction SDNodes (PR #117185)

[James Chesterman via llvm-commits]

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@@ -462,6 +462,16 @@ class TargetLoweringBase {
     return true;
   }
 
+  /// Return true if there is a sign extend on the input to this function. Used
+  /// to determine whether to transform the
+  /// @llvm.experimental.vector.partial.reduce.* intrinsic to
+  /// PARTIAL_REDUCE_SADD or PARTIAL_REDUCE_UADD. It also removes the extend
+  /// from the input. \p Input The 'Input' operand to the
+  /// @llvm.experimental.vector.partial.reduce.* intrinsic.
+  virtual bool isPartialReductionInputSigned(SDValue &Input) const {
+    return false;
+  }
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JamesChesterman wrote:

Also, in the future legalisation patch, I use it to see whether there is an `ISD::MUL` operation done on the input, which leads to different behaviour being done. This searches for the dot product IR pattern, which is target-specific.

https://github.com/llvm/llvm-project/pull/117185