[llvm] [GlobalISel] Correct comment about type vs register class (PR #116083)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 14 17:08:19 PST 2024
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@@ -147,6 +147,16 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
unsigned Opcode = MI.getOpcode();
LLT DstTy = MRI.getType(R);
+ // Handle the case where this is called on a register that does not have a
+ // type constraint (i.e. it's a target instruction with a register class
+ // constraint instead). This is unlikely to occur except by looking through
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arsenm wrote:
You can still have a selected target instruction with a register class constraint, and an LLT. You can always have an LLT. All the LLTs are dropped only after selection is complete. AMDGPU requires the LLT plus the register classes to disambiguate boolean values
https://github.com/llvm/llvm-project/pull/116083
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