[llvm] [GlobalISel] Correct comment about type vs register class (PR #116083)

[Daniel Sanders via llvm-commits]

================
@@ -147,6 +147,16 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
   unsigned Opcode = MI.getOpcode();
   LLT DstTy = MRI.getType(R);
 
+  // Handle the case where this is called on a register that does not have a
+  // type constraint (i.e. it's a target instruction with a register class
+  // constraint instead). This is unlikely to occur except by looking through
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dsandersllvm wrote:

That could be true upstream nowadays although FWIW I don't think it was originally intended that way. The AArch64 tests in KnownBitsTest.cpp at least still mix target instructions without LLT's with gMIR that hasn't been selected yet.
Similarly, in our downstream target we have target instructions without LLT's amongst the gMIR/MIR from the legalizer onwards which is how the new DemandedElt's assertion first hit us. We had some code to conservatively derive DemandedBits from the register class but it was also causing it to ignore the accurate information in LLT's when they were present.

At this point, I think it's probably best to rephrase this comment more generally rather than just tweaking the counter example.

Maybe something like this?:
```
Handle the case where this is called on a register that does not have a type constraint. For example, it may be post-ISel or
this target might not preserve the type when early-selecting instructions.
```

https://github.com/llvm/llvm-project/pull/116083