[llvm] [GlobalISel] Correct comment about type vs register class (PR #116083)

[Daniel Sanders via llvm-commits]

================
@@ -147,6 +147,16 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
   unsigned Opcode = MI.getOpcode();
   LLT DstTy = MRI.getType(R);
 
+  // Handle the case where this is called on a register that does not have a
+  // type constraint (i.e. it's a target instruction with a register class
+  // constraint instead). This is unlikely to occur except by looking through
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dsandersllvm wrote:

I'll update to drop the word 'instead' but it's not the register class part that prevents the LLT. It's the 'target instruction' part. For example, the MOVi32imm in:
```
TEST_F(AArch64GISelMITest, TestKnownBitsCstWithClass) {
  StringRef MIRString = "  %10:gpr32 = MOVi32imm 1\n"
                        "  %4:_(s32) = COPY %10\n";
  setUp(MIRString);
```

LLT and Register Class appearing together happens in gMIR as you say. I think it can happen for certain kinds of pseudo-instructions too (those defined in a similar way to gMIR, we called them 'target-specific generic opcodes' at the time which is a terrible name but nobody had a better one 😀) but not for target instructions or pseudo-instructions defined like instructions

https://github.com/llvm/llvm-project/pull/116083