[llvm] [AArch64] Define high bits of FPR and GPR registers (take 2) (PR #114827)

[Sander de Smalen via llvm-commits]

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@@ -17,13 +17,18 @@
 # CHECK-NEXT:   Single Issue       : false;
 # CHECK-NEXT: SU(1):   renamable $z1 = LD1H renamable $p0, renamable $x2, renamable $x10 :: (load unknown-size, align 1)
 # CHECK-NEXT:   # preds left       : 0
-# CHECK-NEXT:   # succs left       : 4
+# CHECK-NEXT:   # succs left       : 9
 # CHECK-NEXT:   # rdefs left       : 0
 # CHECK-NEXT:   Latency            : 3
 # CHECK-NEXT:   Depth              : 0
 # CHECK-NEXT:   Height             : 7
 # CHECK-NEXT:   Successors:
 # CHECK-NEXT:     SU(7): Out  Latency=1
+# CHECK-NEXT:     SU(7): Out  Latency=1
----------------
sdesmalen-arm wrote:

It's not specific to BUNDLEs, but it is a little specific to how this test was written:
```
BUNDLE implicit-def $z1, implicit-def $q1, implicit-def $d1, implicit-def $s1, implicit-def $h1, implicit-def $b1, implicit $z5, implicit $p0, implicit killed $z4, implicit killed $z3 {
```
the instruction unnecessarily specifies all sub-registers of `z1` as well as `implicit-def`s; `b1, h1, s1, .. q1`, even though `implicit-def $z1` would have been sufficient. When I remove the implicit-def for the sub-registers, the scheduler no longer creates the extra out-dependences.

I can see that the scheduler goes through all register units for a given register to create dependences. Before this change there was only a single RegUnit for all registers `z1, q1, s1, .. b1`, whereas now there are 6 separate regunits, hence the extra dependences.

I'd need to dig a bit further to understand why the scheduler adds these when the implicit-def operands are present, although this isn't a common case for regular instructions (it may be more common for BUNDLE's?) so don't think this has much of an effect in practice. If you're satisfied with that answer, I'd prefer to move forward with the patch as-is, since I've got a few more follow-up patches to fix up other things. I'll look further into it anyway, just in case there's something that needs fixing.

https://github.com/llvm/llvm-project/pull/114827