[llvm] [AArch64] Define high bits of FPR and GPR registers (take 2) (PR #114827)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff ae0ab2486287a914d9506ac2ff73e41063bf9a7e 4ef35e2d76fff1e642e67fb12a5755eae6d1417f --extensions cpp,h -- llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp llvm/include/llvm/MC/MCRegisterInfo.h llvm/lib/MCA/HardwareUnits/RegisterFile.cpp llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp llvm/utils/TableGen/RegisterInfoEmitter.cpp
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/include/llvm/MC/MCRegisterInfo.h b/llvm/include/llvm/MC/MCRegisterInfo.h
index 6f202ba199..73f29d0f52 100644
--- a/llvm/include/llvm/MC/MCRegisterInfo.h
+++ b/llvm/include/llvm/MC/MCRegisterInfo.h
@@ -399,9 +399,9 @@ public:
   /// Returns true if the given register is constant.
   bool isConstant(MCRegister RegNo) const { return get(RegNo).IsConstant; }
 
-  /// Returns true if the given register is artificial, which means it represents
-  /// a regunit that is not separately addressable but still needs to be modelled,
-  /// such as the top 16-bits of a 32-bit GPR.
+  /// Returns true if the given register is artificial, which means it
+  /// represents a regunit that is not separately addressable but still needs to
+  /// be modelled, such as the top 16-bits of a 32-bit GPR.
   bool isArtificial(MCRegister RegNo) const { return get(RegNo).IsArtificial; }
 
   /// Return the number of registers this target has (useful for

``````````

</details>


https://github.com/llvm/llvm-project/pull/114827