[llvm] [AArch64] Define high bits of FPR and GPR registers (take 2) (PR #114827)
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 12 01:07:42 PST 2024
https://github.com/sdesmalen-arm updated https://github.com/llvm/llvm-project/pull/114827
>From b325481cf41485b2dd200312b6a6479b622741a3 Mon Sep 17 00:00:00 2001
From: Sander de Smalen <sander.desmalen at arm.com>
Date: Wed, 23 Oct 2024 16:52:19 +0100
Subject: [PATCH 1/7] [AArch64] Define high bits of FPR and GPR registers.
This is a step towards enabling subreg liveness tracking for AArch64, which
requires that registers are fully covered by their subregisters, as
covered here #109797.
There are several changes in this patch:
* AArch64RegisterInfo.td and tests: Define the high bits like B0_HI,
H0_HI, S0_HI, D0_HI, Q0_HI. Because the bits must be defined by some
register class, this added a register class which meant that we had
to update 'magic numbers' in several tests.
The use of ComposedSubRegIndex helped 'compress' the number
of bits required for the lanemask. The correctness of the masks
is tested by an explicit unit tests.
* LoadStoreOptimizer: previously 'HasDisjunctSubRegs' was only true for
register tuples, but with this change to describe the high bits, a
register like 'D0' will also have 'HasDisjunctSubRegs' set to true
(because it's fullly covered by S0 and S0_HI). The fix here is to
explicitly test if the register class is one of the known D/Q/Z
tuples.
* TableGen: The handling of the isArtificial flag was entirely broken.
Skipping out too early from some of the loops led to incorrect
internal representation of the (sub)register(index) hierarchy, and
thus resulted in incorrect TableGen info.
---
.../AArch64/AArch64LoadStoreOptimizer.cpp | 5 +-
.../Target/AArch64/AArch64RegisterInfo.cpp | 59 ++-
.../lib/Target/AArch64/AArch64RegisterInfo.td | 497 +++++++++---------
.../AArch64/GlobalISel/regbank-inlineasm.mir | 8 +-
llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll | 22 +-
.../AArch64/blr-bti-preserves-operands.mir | 2 +-
.../emit_fneg_with_non_register_operand.mir | 8 +-
.../AArch64/expand-blr-rvmarker-pseudo.mir | 12 +-
.../test/CodeGen/AArch64/ldrpre-ldr-merge.mir | 60 +--
.../AArch64/machine-outliner-calls.mir | 2 +-
llvm/test/CodeGen/AArch64/misched-bundle.mir | 26 +-
.../misched-detail-resource-booking-01.mir | 12 +
.../misched-detail-resource-booking-02.mir | 5 +-
.../CodeGen/AArch64/peephole-insvigpr.mir | 4 +-
llvm/test/CodeGen/AArch64/preserve.ll | 7 +-
.../test/CodeGen/AArch64/strpre-str-merge.mir | 28 +-
.../sve-intrinsics-int-arith-merging.mir | 2 +-
.../sve-intrinsics-int-binaryComm-merging.mir | 2 +-
...trinsics-int-binaryCommWithRev-merging.mir | 2 +-
.../AArch64/AArch64RegisterInfoTest.cpp | 148 ++++++
llvm/unittests/Target/AArch64/CMakeLists.txt | 1 +
llvm/utils/TableGen/RegisterInfoEmitter.cpp | 1 +
22 files changed, 592 insertions(+), 321 deletions(-)
create mode 100644 llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index 1a9e5899892a1b..b051122609883f 100644
--- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -1541,7 +1541,10 @@ static bool canRenameMOP(const MachineOperand &MOP,
// Note that this relies on the structure of the AArch64 register file. In
// particular, a subregister cannot be written without overwriting the
// whole register.
- if (RegClass->HasDisjunctSubRegs) {
+ if (RegClass->HasDisjunctSubRegs && RegClass->CoveredBySubRegs &&
+ (TRI->getSubRegisterClass(RegClass, AArch64::dsub0) ||
+ TRI->getSubRegisterClass(RegClass, AArch64::qsub0) ||
+ TRI->getSubRegisterClass(RegClass, AArch64::zsub0))) {
LLVM_DEBUG(
dbgs()
<< " Cannot rename operands with multiple disjunct subregisters ("
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index 18290dd5f32df9..1ef75c6e02e8c7 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -424,6 +424,58 @@ AArch64RegisterInfo::explainReservedReg(const MachineFunction &MF,
return {};
}
+static SmallVector<MCPhysReg> ReservedHi = {
+ AArch64::B0_HI, AArch64::B1_HI, AArch64::B2_HI, AArch64::B3_HI,
+ AArch64::B4_HI, AArch64::B5_HI, AArch64::B6_HI, AArch64::B7_HI,
+ AArch64::B8_HI, AArch64::B9_HI, AArch64::B10_HI, AArch64::B11_HI,
+ AArch64::B12_HI, AArch64::B13_HI, AArch64::B14_HI, AArch64::B15_HI,
+ AArch64::B16_HI, AArch64::B17_HI, AArch64::B18_HI, AArch64::B19_HI,
+ AArch64::B20_HI, AArch64::B21_HI, AArch64::B22_HI, AArch64::B23_HI,
+ AArch64::B24_HI, AArch64::B25_HI, AArch64::B26_HI, AArch64::B27_HI,
+ AArch64::B28_HI, AArch64::B29_HI, AArch64::B30_HI, AArch64::B31_HI,
+ AArch64::H0_HI, AArch64::H1_HI, AArch64::H2_HI, AArch64::H3_HI,
+ AArch64::H4_HI, AArch64::H5_HI, AArch64::H6_HI, AArch64::H7_HI,
+ AArch64::H8_HI, AArch64::H9_HI, AArch64::H10_HI, AArch64::H11_HI,
+ AArch64::H12_HI, AArch64::H13_HI, AArch64::H14_HI, AArch64::H15_HI,
+ AArch64::H16_HI, AArch64::H17_HI, AArch64::H18_HI, AArch64::H19_HI,
+ AArch64::H20_HI, AArch64::H21_HI, AArch64::H22_HI, AArch64::H23_HI,
+ AArch64::H24_HI, AArch64::H25_HI, AArch64::H26_HI, AArch64::H27_HI,
+ AArch64::H28_HI, AArch64::H29_HI, AArch64::H30_HI, AArch64::H31_HI,
+ AArch64::S0_HI, AArch64::S1_HI, AArch64::S2_HI, AArch64::S3_HI,
+ AArch64::S4_HI, AArch64::S5_HI, AArch64::S6_HI, AArch64::S7_HI,
+ AArch64::S8_HI, AArch64::S9_HI, AArch64::S10_HI, AArch64::S11_HI,
+ AArch64::S12_HI, AArch64::S13_HI, AArch64::S14_HI, AArch64::S15_HI,
+ AArch64::S16_HI, AArch64::S17_HI, AArch64::S18_HI, AArch64::S19_HI,
+ AArch64::S20_HI, AArch64::S21_HI, AArch64::S22_HI, AArch64::S23_HI,
+ AArch64::S24_HI, AArch64::S25_HI, AArch64::S26_HI, AArch64::S27_HI,
+ AArch64::S28_HI, AArch64::S29_HI, AArch64::S30_HI, AArch64::S31_HI,
+ AArch64::D0_HI, AArch64::D1_HI, AArch64::D2_HI, AArch64::D3_HI,
+ AArch64::D4_HI, AArch64::D5_HI, AArch64::D6_HI, AArch64::D7_HI,
+ AArch64::D8_HI, AArch64::D9_HI, AArch64::D10_HI, AArch64::D11_HI,
+ AArch64::D12_HI, AArch64::D13_HI, AArch64::D14_HI, AArch64::D15_HI,
+ AArch64::D16_HI, AArch64::D17_HI, AArch64::D18_HI, AArch64::D19_HI,
+ AArch64::D20_HI, AArch64::D21_HI, AArch64::D22_HI, AArch64::D23_HI,
+ AArch64::D24_HI, AArch64::D25_HI, AArch64::D26_HI, AArch64::D27_HI,
+ AArch64::D28_HI, AArch64::D29_HI, AArch64::D30_HI, AArch64::D31_HI,
+ AArch64::Q0_HI, AArch64::Q1_HI, AArch64::Q2_HI, AArch64::Q3_HI,
+ AArch64::Q4_HI, AArch64::Q5_HI, AArch64::Q6_HI, AArch64::Q7_HI,
+ AArch64::Q8_HI, AArch64::Q9_HI, AArch64::Q10_HI, AArch64::Q11_HI,
+ AArch64::Q12_HI, AArch64::Q13_HI, AArch64::Q14_HI, AArch64::Q15_HI,
+ AArch64::Q16_HI, AArch64::Q17_HI, AArch64::Q18_HI, AArch64::Q19_HI,
+ AArch64::Q20_HI, AArch64::Q21_HI, AArch64::Q22_HI, AArch64::Q23_HI,
+ AArch64::Q24_HI, AArch64::Q25_HI, AArch64::Q26_HI, AArch64::Q27_HI,
+ AArch64::Q28_HI, AArch64::Q29_HI, AArch64::Q30_HI, AArch64::Q31_HI,
+ AArch64::W0_HI, AArch64::W1_HI, AArch64::W2_HI, AArch64::W3_HI,
+ AArch64::W4_HI, AArch64::W5_HI, AArch64::W6_HI, AArch64::W7_HI,
+ AArch64::W8_HI, AArch64::W9_HI, AArch64::W10_HI, AArch64::W11_HI,
+ AArch64::W12_HI, AArch64::W13_HI, AArch64::W14_HI, AArch64::W15_HI,
+ AArch64::W16_HI, AArch64::W17_HI, AArch64::W18_HI, AArch64::W19_HI,
+ AArch64::W20_HI, AArch64::W21_HI, AArch64::W22_HI, AArch64::W23_HI,
+ AArch64::W24_HI, AArch64::W25_HI, AArch64::W26_HI, AArch64::W27_HI,
+ AArch64::W28_HI, AArch64::W29_HI, AArch64::W30_HI, AArch64::WSP_HI,
+ AArch64::WZR_HI
+ };
+
BitVector
AArch64RegisterInfo::getStrictlyReservedRegs(const MachineFunction &MF) const {
const AArch64FrameLowering *TFI = getFrameLowering(MF);
@@ -490,7 +542,10 @@ AArch64RegisterInfo::getStrictlyReservedRegs(const MachineFunction &MF) const {
markSuperRegs(Reserved, AArch64::W28);
}
- assert(checkAllSuperRegsMarked(Reserved));
+ for (Register R : ReservedHi)
+ Reserved.set(R);
+
+ assert(checkAllSuperRegsMarked(Reserved, ReservedHi));
return Reserved;
}
@@ -514,7 +569,7 @@ AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
markSuperRegs(Reserved, AArch64::LR);
}
- assert(checkAllSuperRegsMarked(Reserved));
+ assert(checkAllSuperRegsMarked(Reserved, ReservedHi));
return Reserved;
}
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
index 4117d74d10c1e7..5f7f6aa7a7bf99 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -20,33 +20,39 @@ class AArch64Reg<bits<16> enc, string n, list<Register> subregs = [],
let Namespace = "AArch64" in {
// SubRegIndexes for GPR registers
- def sub_32 : SubRegIndex<32>;
- def sube64 : SubRegIndex<64>;
- def subo64 : SubRegIndex<64>;
- def sube32 : SubRegIndex<32>;
- def subo32 : SubRegIndex<32>;
+ def sub_32 : SubRegIndex<32, 0>;
+ def sub_32_hi: SubRegIndex<32, 32>;
+ def sube64 : SubRegIndex<64>;
+ def subo64 : SubRegIndex<64>;
+ def sube32 : SubRegIndex<32>;
+ def subo32 : SubRegIndex<32>;
// SubRegIndexes for FPR/Vector registers
- def bsub : SubRegIndex<8>;
- def hsub : SubRegIndex<16>;
- def ssub : SubRegIndex<32>;
- def dsub : SubRegIndex<64>;
- def zsub : SubRegIndex<128>;
+ def bsub : SubRegIndex<8, 0>;
+ def bsub_hi : SubRegIndex<8, 8>;
+ def hsub : SubRegIndex<16, 0>;
+ def hsub_hi : SubRegIndex<16, 16>;
+ def ssub : SubRegIndex<32, 0>;
+ def ssub_hi : SubRegIndex<32, 32>;
+ def dsub : SubRegIndex<64, 0>;
+ def dsub_hi : SubRegIndex<64, 64>;
+ def zsub : SubRegIndex<128, 0>;
+ def zsub_hi : SubRegIndex<-1, 128>;
// Note: Code depends on these having consecutive numbers
- def zsub0 : SubRegIndex<128, -1>;
- def zsub1 : SubRegIndex<128, -1>;
- def zsub2 : SubRegIndex<128, -1>;
- def zsub3 : SubRegIndex<128, -1>;
- // Note: Code depends on these having consecutive numbers
- def dsub0 : SubRegIndex<64>;
- def dsub1 : SubRegIndex<64>;
- def dsub2 : SubRegIndex<64>;
- def dsub3 : SubRegIndex<64>;
+ def zsub0 : SubRegIndex<-1>;
+ def zsub1 : SubRegIndex<-1>;
+ def zsub2 : SubRegIndex<-1>;
+ def zsub3 : SubRegIndex<-1>;
// Note: Code depends on these having consecutive numbers
def qsub0 : SubRegIndex<128>;
- def qsub1 : SubRegIndex<128>;
- def qsub2 : SubRegIndex<128>;
- def qsub3 : SubRegIndex<128>;
+ def qsub1 : ComposedSubRegIndex<zsub1, zsub>;
+ def qsub2 : ComposedSubRegIndex<zsub2, zsub>;
+ def qsub3 : ComposedSubRegIndex<zsub3, zsub>;
+ // Note: Code depends on these having consecutive numbers
+ def dsub0 : SubRegIndex<64>;
+ def dsub1 : ComposedSubRegIndex<qsub1, dsub>;
+ def dsub2 : ComposedSubRegIndex<qsub2, dsub>;
+ def dsub3 : ComposedSubRegIndex<qsub3, dsub>;
// SubRegIndexes for SME Matrix tiles
def zasubb : SubRegIndex<2048>; // (16 x 16)/1 bytes = 2048 bits
@@ -60,10 +66,10 @@ let Namespace = "AArch64" in {
def zasubq1 : SubRegIndex<128>; // (16 x 16)/16 bytes = 128 bits
// SubRegIndexes for SVE Predicates
- def psub : SubRegIndex<16>;
+ def psub : SubRegIndex<-1>;
// Note: Code depends on these having consecutive numbers
- def psub0 : SubRegIndex<16, -1>;
- def psub1 : SubRegIndex<16, -1>;
+ def psub0 : SubRegIndex<-1>;
+ def psub1 : SubRegIndex<-1>;
}
let Namespace = "AArch64" in {
@@ -74,6 +80,14 @@ let Namespace = "AArch64" in {
//===----------------------------------------------------------------------===//
// Registers
//===----------------------------------------------------------------------===//
+
+foreach i = 0-30 in {
+ // Define W0_HI, W1_HI, .. W30_HI
+ def W#i#_HI : AArch64Reg<-1, "w"#i#"_hi"> { let isArtificial = 1; }
+}
+def WSP_HI : AArch64Reg<-1, "wsp_hi"> { let isArtificial = 1; }
+def WZR_HI : AArch64Reg<-1, "wzr_hi"> { let isArtificial = 1; }
+
def W0 : AArch64Reg<0, "w0" >, DwarfRegNum<[0]>;
def W1 : AArch64Reg<1, "w1" >, DwarfRegNum<[1]>;
def W2 : AArch64Reg<2, "w2" >, DwarfRegNum<[2]>;
@@ -106,44 +120,42 @@ def W28 : AArch64Reg<28, "w28">, DwarfRegNum<[28]>;
def W29 : AArch64Reg<29, "w29">, DwarfRegNum<[29]>;
def W30 : AArch64Reg<30, "w30">, DwarfRegNum<[30]>;
def WSP : AArch64Reg<31, "wsp">, DwarfRegNum<[31]>;
-let isConstant = true in
-def WZR : AArch64Reg<31, "wzr">, DwarfRegAlias<WSP>;
-
-let SubRegIndices = [sub_32] in {
-def X0 : AArch64Reg<0, "x0", [W0]>, DwarfRegAlias<W0>;
-def X1 : AArch64Reg<1, "x1", [W1]>, DwarfRegAlias<W1>;
-def X2 : AArch64Reg<2, "x2", [W2]>, DwarfRegAlias<W2>;
-def X3 : AArch64Reg<3, "x3", [W3]>, DwarfRegAlias<W3>;
-def X4 : AArch64Reg<4, "x4", [W4]>, DwarfRegAlias<W4>;
-def X5 : AArch64Reg<5, "x5", [W5]>, DwarfRegAlias<W5>;
-def X6 : AArch64Reg<6, "x6", [W6]>, DwarfRegAlias<W6>;
-def X7 : AArch64Reg<7, "x7", [W7]>, DwarfRegAlias<W7>;
-def X8 : AArch64Reg<8, "x8", [W8]>, DwarfRegAlias<W8>;
-def X9 : AArch64Reg<9, "x9", [W9]>, DwarfRegAlias<W9>;
-def X10 : AArch64Reg<10, "x10", [W10]>, DwarfRegAlias<W10>;
-def X11 : AArch64Reg<11, "x11", [W11]>, DwarfRegAlias<W11>;
-def X12 : AArch64Reg<12, "x12", [W12]>, DwarfRegAlias<W12>;
-def X13 : AArch64Reg<13, "x13", [W13]>, DwarfRegAlias<W13>;
-def X14 : AArch64Reg<14, "x14", [W14]>, DwarfRegAlias<W14>;
-def X15 : AArch64Reg<15, "x15", [W15]>, DwarfRegAlias<W15>;
-def X16 : AArch64Reg<16, "x16", [W16]>, DwarfRegAlias<W16>;
-def X17 : AArch64Reg<17, "x17", [W17]>, DwarfRegAlias<W17>;
-def X18 : AArch64Reg<18, "x18", [W18]>, DwarfRegAlias<W18>;
-def X19 : AArch64Reg<19, "x19", [W19]>, DwarfRegAlias<W19>;
-def X20 : AArch64Reg<20, "x20", [W20]>, DwarfRegAlias<W20>;
-def X21 : AArch64Reg<21, "x21", [W21]>, DwarfRegAlias<W21>;
-def X22 : AArch64Reg<22, "x22", [W22]>, DwarfRegAlias<W22>;
-def X23 : AArch64Reg<23, "x23", [W23]>, DwarfRegAlias<W23>;
-def X24 : AArch64Reg<24, "x24", [W24]>, DwarfRegAlias<W24>;
-def X25 : AArch64Reg<25, "x25", [W25]>, DwarfRegAlias<W25>;
-def X26 : AArch64Reg<26, "x26", [W26]>, DwarfRegAlias<W26>;
-def X27 : AArch64Reg<27, "x27", [W27]>, DwarfRegAlias<W27>;
-def X28 : AArch64Reg<28, "x28", [W28]>, DwarfRegAlias<W28>;
-def FP : AArch64Reg<29, "x29", [W29]>, DwarfRegAlias<W29>;
-def LR : AArch64Reg<30, "x30", [W30]>, DwarfRegAlias<W30>;
-def SP : AArch64Reg<31, "sp", [WSP]>, DwarfRegAlias<WSP>;
-let isConstant = true in
-def XZR : AArch64Reg<31, "xzr", [WZR]>, DwarfRegAlias<WSP>;
+def WZR : AArch64Reg<31, "wzr">, DwarfRegAlias<WSP> { let isConstant = true; }
+
+let SubRegIndices = [sub_32, sub_32_hi], CoveredBySubRegs = 1 in {
+def X0 : AArch64Reg<0, "x0", [W0, W0_HI]>, DwarfRegAlias<W0>;
+def X1 : AArch64Reg<1, "x1", [W1, W1_HI]>, DwarfRegAlias<W1>;
+def X2 : AArch64Reg<2, "x2", [W2, W2_HI]>, DwarfRegAlias<W2>;
+def X3 : AArch64Reg<3, "x3", [W3, W3_HI]>, DwarfRegAlias<W3>;
+def X4 : AArch64Reg<4, "x4", [W4, W4_HI]>, DwarfRegAlias<W4>;
+def X5 : AArch64Reg<5, "x5", [W5, W5_HI]>, DwarfRegAlias<W5>;
+def X6 : AArch64Reg<6, "x6", [W6, W6_HI]>, DwarfRegAlias<W6>;
+def X7 : AArch64Reg<7, "x7", [W7, W7_HI]>, DwarfRegAlias<W7>;
+def X8 : AArch64Reg<8, "x8", [W8, W8_HI]>, DwarfRegAlias<W8>;
+def X9 : AArch64Reg<9, "x9", [W9, W9_HI]>, DwarfRegAlias<W9>;
+def X10 : AArch64Reg<10, "x10", [W10, W10_HI]>, DwarfRegAlias<W10>;
+def X11 : AArch64Reg<11, "x11", [W11, W11_HI]>, DwarfRegAlias<W11>;
+def X12 : AArch64Reg<12, "x12", [W12, W12_HI]>, DwarfRegAlias<W12>;
+def X13 : AArch64Reg<13, "x13", [W13, W13_HI]>, DwarfRegAlias<W13>;
+def X14 : AArch64Reg<14, "x14", [W14, W14_HI]>, DwarfRegAlias<W14>;
+def X15 : AArch64Reg<15, "x15", [W15, W15_HI]>, DwarfRegAlias<W15>;
+def X16 : AArch64Reg<16, "x16", [W16, W16_HI]>, DwarfRegAlias<W16>;
+def X17 : AArch64Reg<17, "x17", [W17, W17_HI]>, DwarfRegAlias<W17>;
+def X18 : AArch64Reg<18, "x18", [W18, W18_HI]>, DwarfRegAlias<W18>;
+def X19 : AArch64Reg<19, "x19", [W19, W19_HI]>, DwarfRegAlias<W19>;
+def X20 : AArch64Reg<20, "x20", [W20, W20_HI]>, DwarfRegAlias<W20>;
+def X21 : AArch64Reg<21, "x21", [W21, W21_HI]>, DwarfRegAlias<W21>;
+def X22 : AArch64Reg<22, "x22", [W22, W22_HI]>, DwarfRegAlias<W22>;
+def X23 : AArch64Reg<23, "x23", [W23, W23_HI]>, DwarfRegAlias<W23>;
+def X24 : AArch64Reg<24, "x24", [W24, W24_HI]>, DwarfRegAlias<W24>;
+def X25 : AArch64Reg<25, "x25", [W25, W25_HI]>, DwarfRegAlias<W25>;
+def X26 : AArch64Reg<26, "x26", [W26, W26_HI]>, DwarfRegAlias<W26>;
+def X27 : AArch64Reg<27, "x27", [W27, W27_HI]>, DwarfRegAlias<W27>;
+def X28 : AArch64Reg<28, "x28", [W28, W28_HI]>, DwarfRegAlias<W28>;
+def FP : AArch64Reg<29, "x29", [W29, W29_HI]>, DwarfRegAlias<W29>;
+def LR : AArch64Reg<30, "x30", [W30, W30_HI]>, DwarfRegAlias<W30>;
+def SP : AArch64Reg<31, "sp", [WSP, WSP_HI]>, DwarfRegAlias<WSP>;
+def XZR : AArch64Reg<31, "xzr", [WZR, WZR_HI]>, DwarfRegAlias<WSP> { let isConstant = true; }
}
// Condition code register.
@@ -290,6 +302,14 @@ def CCR : RegisterClass<"AArch64", [i32], 32, (add NZCV)> {
// Floating Point Scalar Registers
//===----------------------------------------------------------------------===//
+foreach i = 0-31 in {
+ def B#i#_HI : AArch64Reg<-1, "b"#i#"_hi"> { let isArtificial = 1; }
+ def H#i#_HI : AArch64Reg<-1, "h"#i#"_hi"> { let isArtificial = 1; }
+ def S#i#_HI : AArch64Reg<-1, "s"#i#"_hi"> { let isArtificial = 1; }
+ def D#i#_HI : AArch64Reg<-1, "d"#i#"_hi"> { let isArtificial = 1; }
+ def Q#i#_HI : AArch64Reg<-1, "q"#i#"_hi"> { let isArtificial = 1; }
+}
+
def B0 : AArch64Reg<0, "b0">, DwarfRegNum<[64]>;
def B1 : AArch64Reg<1, "b1">, DwarfRegNum<[65]>;
def B2 : AArch64Reg<2, "b2">, DwarfRegNum<[66]>;
@@ -323,144 +343,144 @@ def B29 : AArch64Reg<29, "b29">, DwarfRegNum<[93]>;
def B30 : AArch64Reg<30, "b30">, DwarfRegNum<[94]>;
def B31 : AArch64Reg<31, "b31">, DwarfRegNum<[95]>;
-let SubRegIndices = [bsub] in {
-def H0 : AArch64Reg<0, "h0", [B0]>, DwarfRegAlias<B0>;
-def H1 : AArch64Reg<1, "h1", [B1]>, DwarfRegAlias<B1>;
-def H2 : AArch64Reg<2, "h2", [B2]>, DwarfRegAlias<B2>;
-def H3 : AArch64Reg<3, "h3", [B3]>, DwarfRegAlias<B3>;
-def H4 : AArch64Reg<4, "h4", [B4]>, DwarfRegAlias<B4>;
-def H5 : AArch64Reg<5, "h5", [B5]>, DwarfRegAlias<B5>;
-def H6 : AArch64Reg<6, "h6", [B6]>, DwarfRegAlias<B6>;
-def H7 : AArch64Reg<7, "h7", [B7]>, DwarfRegAlias<B7>;
-def H8 : AArch64Reg<8, "h8", [B8]>, DwarfRegAlias<B8>;
-def H9 : AArch64Reg<9, "h9", [B9]>, DwarfRegAlias<B9>;
-def H10 : AArch64Reg<10, "h10", [B10]>, DwarfRegAlias<B10>;
-def H11 : AArch64Reg<11, "h11", [B11]>, DwarfRegAlias<B11>;
-def H12 : AArch64Reg<12, "h12", [B12]>, DwarfRegAlias<B12>;
-def H13 : AArch64Reg<13, "h13", [B13]>, DwarfRegAlias<B13>;
-def H14 : AArch64Reg<14, "h14", [B14]>, DwarfRegAlias<B14>;
-def H15 : AArch64Reg<15, "h15", [B15]>, DwarfRegAlias<B15>;
-def H16 : AArch64Reg<16, "h16", [B16]>, DwarfRegAlias<B16>;
-def H17 : AArch64Reg<17, "h17", [B17]>, DwarfRegAlias<B17>;
-def H18 : AArch64Reg<18, "h18", [B18]>, DwarfRegAlias<B18>;
-def H19 : AArch64Reg<19, "h19", [B19]>, DwarfRegAlias<B19>;
-def H20 : AArch64Reg<20, "h20", [B20]>, DwarfRegAlias<B20>;
-def H21 : AArch64Reg<21, "h21", [B21]>, DwarfRegAlias<B21>;
-def H22 : AArch64Reg<22, "h22", [B22]>, DwarfRegAlias<B22>;
-def H23 : AArch64Reg<23, "h23", [B23]>, DwarfRegAlias<B23>;
-def H24 : AArch64Reg<24, "h24", [B24]>, DwarfRegAlias<B24>;
-def H25 : AArch64Reg<25, "h25", [B25]>, DwarfRegAlias<B25>;
-def H26 : AArch64Reg<26, "h26", [B26]>, DwarfRegAlias<B26>;
-def H27 : AArch64Reg<27, "h27", [B27]>, DwarfRegAlias<B27>;
-def H28 : AArch64Reg<28, "h28", [B28]>, DwarfRegAlias<B28>;
-def H29 : AArch64Reg<29, "h29", [B29]>, DwarfRegAlias<B29>;
-def H30 : AArch64Reg<30, "h30", [B30]>, DwarfRegAlias<B30>;
-def H31 : AArch64Reg<31, "h31", [B31]>, DwarfRegAlias<B31>;
-}
-
-let SubRegIndices = [hsub] in {
-def S0 : AArch64Reg<0, "s0", [H0]>, DwarfRegAlias<B0>;
-def S1 : AArch64Reg<1, "s1", [H1]>, DwarfRegAlias<B1>;
-def S2 : AArch64Reg<2, "s2", [H2]>, DwarfRegAlias<B2>;
-def S3 : AArch64Reg<3, "s3", [H3]>, DwarfRegAlias<B3>;
-def S4 : AArch64Reg<4, "s4", [H4]>, DwarfRegAlias<B4>;
-def S5 : AArch64Reg<5, "s5", [H5]>, DwarfRegAlias<B5>;
-def S6 : AArch64Reg<6, "s6", [H6]>, DwarfRegAlias<B6>;
-def S7 : AArch64Reg<7, "s7", [H7]>, DwarfRegAlias<B7>;
-def S8 : AArch64Reg<8, "s8", [H8]>, DwarfRegAlias<B8>;
-def S9 : AArch64Reg<9, "s9", [H9]>, DwarfRegAlias<B9>;
-def S10 : AArch64Reg<10, "s10", [H10]>, DwarfRegAlias<B10>;
-def S11 : AArch64Reg<11, "s11", [H11]>, DwarfRegAlias<B11>;
-def S12 : AArch64Reg<12, "s12", [H12]>, DwarfRegAlias<B12>;
-def S13 : AArch64Reg<13, "s13", [H13]>, DwarfRegAlias<B13>;
-def S14 : AArch64Reg<14, "s14", [H14]>, DwarfRegAlias<B14>;
-def S15 : AArch64Reg<15, "s15", [H15]>, DwarfRegAlias<B15>;
-def S16 : AArch64Reg<16, "s16", [H16]>, DwarfRegAlias<B16>;
-def S17 : AArch64Reg<17, "s17", [H17]>, DwarfRegAlias<B17>;
-def S18 : AArch64Reg<18, "s18", [H18]>, DwarfRegAlias<B18>;
-def S19 : AArch64Reg<19, "s19", [H19]>, DwarfRegAlias<B19>;
-def S20 : AArch64Reg<20, "s20", [H20]>, DwarfRegAlias<B20>;
-def S21 : AArch64Reg<21, "s21", [H21]>, DwarfRegAlias<B21>;
-def S22 : AArch64Reg<22, "s22", [H22]>, DwarfRegAlias<B22>;
-def S23 : AArch64Reg<23, "s23", [H23]>, DwarfRegAlias<B23>;
-def S24 : AArch64Reg<24, "s24", [H24]>, DwarfRegAlias<B24>;
-def S25 : AArch64Reg<25, "s25", [H25]>, DwarfRegAlias<B25>;
-def S26 : AArch64Reg<26, "s26", [H26]>, DwarfRegAlias<B26>;
-def S27 : AArch64Reg<27, "s27", [H27]>, DwarfRegAlias<B27>;
-def S28 : AArch64Reg<28, "s28", [H28]>, DwarfRegAlias<B28>;
-def S29 : AArch64Reg<29, "s29", [H29]>, DwarfRegAlias<B29>;
-def S30 : AArch64Reg<30, "s30", [H30]>, DwarfRegAlias<B30>;
-def S31 : AArch64Reg<31, "s31", [H31]>, DwarfRegAlias<B31>;
-}
-
-let SubRegIndices = [ssub], RegAltNameIndices = [vreg, vlist1] in {
-def D0 : AArch64Reg<0, "d0", [S0], ["v0", ""]>, DwarfRegAlias<B0>;
-def D1 : AArch64Reg<1, "d1", [S1], ["v1", ""]>, DwarfRegAlias<B1>;
-def D2 : AArch64Reg<2, "d2", [S2], ["v2", ""]>, DwarfRegAlias<B2>;
-def D3 : AArch64Reg<3, "d3", [S3], ["v3", ""]>, DwarfRegAlias<B3>;
-def D4 : AArch64Reg<4, "d4", [S4], ["v4", ""]>, DwarfRegAlias<B4>;
-def D5 : AArch64Reg<5, "d5", [S5], ["v5", ""]>, DwarfRegAlias<B5>;
-def D6 : AArch64Reg<6, "d6", [S6], ["v6", ""]>, DwarfRegAlias<B6>;
-def D7 : AArch64Reg<7, "d7", [S7], ["v7", ""]>, DwarfRegAlias<B7>;
-def D8 : AArch64Reg<8, "d8", [S8], ["v8", ""]>, DwarfRegAlias<B8>;
-def D9 : AArch64Reg<9, "d9", [S9], ["v9", ""]>, DwarfRegAlias<B9>;
-def D10 : AArch64Reg<10, "d10", [S10], ["v10", ""]>, DwarfRegAlias<B10>;
-def D11 : AArch64Reg<11, "d11", [S11], ["v11", ""]>, DwarfRegAlias<B11>;
-def D12 : AArch64Reg<12, "d12", [S12], ["v12", ""]>, DwarfRegAlias<B12>;
-def D13 : AArch64Reg<13, "d13", [S13], ["v13", ""]>, DwarfRegAlias<B13>;
-def D14 : AArch64Reg<14, "d14", [S14], ["v14", ""]>, DwarfRegAlias<B14>;
-def D15 : AArch64Reg<15, "d15", [S15], ["v15", ""]>, DwarfRegAlias<B15>;
-def D16 : AArch64Reg<16, "d16", [S16], ["v16", ""]>, DwarfRegAlias<B16>;
-def D17 : AArch64Reg<17, "d17", [S17], ["v17", ""]>, DwarfRegAlias<B17>;
-def D18 : AArch64Reg<18, "d18", [S18], ["v18", ""]>, DwarfRegAlias<B18>;
-def D19 : AArch64Reg<19, "d19", [S19], ["v19", ""]>, DwarfRegAlias<B19>;
-def D20 : AArch64Reg<20, "d20", [S20], ["v20", ""]>, DwarfRegAlias<B20>;
-def D21 : AArch64Reg<21, "d21", [S21], ["v21", ""]>, DwarfRegAlias<B21>;
-def D22 : AArch64Reg<22, "d22", [S22], ["v22", ""]>, DwarfRegAlias<B22>;
-def D23 : AArch64Reg<23, "d23", [S23], ["v23", ""]>, DwarfRegAlias<B23>;
-def D24 : AArch64Reg<24, "d24", [S24], ["v24", ""]>, DwarfRegAlias<B24>;
-def D25 : AArch64Reg<25, "d25", [S25], ["v25", ""]>, DwarfRegAlias<B25>;
-def D26 : AArch64Reg<26, "d26", [S26], ["v26", ""]>, DwarfRegAlias<B26>;
-def D27 : AArch64Reg<27, "d27", [S27], ["v27", ""]>, DwarfRegAlias<B27>;
-def D28 : AArch64Reg<28, "d28", [S28], ["v28", ""]>, DwarfRegAlias<B28>;
-def D29 : AArch64Reg<29, "d29", [S29], ["v29", ""]>, DwarfRegAlias<B29>;
-def D30 : AArch64Reg<30, "d30", [S30], ["v30", ""]>, DwarfRegAlias<B30>;
-def D31 : AArch64Reg<31, "d31", [S31], ["v31", ""]>, DwarfRegAlias<B31>;
-}
-
-let SubRegIndices = [dsub], RegAltNameIndices = [vreg, vlist1] in {
-def Q0 : AArch64Reg<0, "q0", [D0], ["v0", ""]>, DwarfRegAlias<B0>;
-def Q1 : AArch64Reg<1, "q1", [D1], ["v1", ""]>, DwarfRegAlias<B1>;
-def Q2 : AArch64Reg<2, "q2", [D2], ["v2", ""]>, DwarfRegAlias<B2>;
-def Q3 : AArch64Reg<3, "q3", [D3], ["v3", ""]>, DwarfRegAlias<B3>;
-def Q4 : AArch64Reg<4, "q4", [D4], ["v4", ""]>, DwarfRegAlias<B4>;
-def Q5 : AArch64Reg<5, "q5", [D5], ["v5", ""]>, DwarfRegAlias<B5>;
-def Q6 : AArch64Reg<6, "q6", [D6], ["v6", ""]>, DwarfRegAlias<B6>;
-def Q7 : AArch64Reg<7, "q7", [D7], ["v7", ""]>, DwarfRegAlias<B7>;
-def Q8 : AArch64Reg<8, "q8", [D8], ["v8", ""]>, DwarfRegAlias<B8>;
-def Q9 : AArch64Reg<9, "q9", [D9], ["v9", ""]>, DwarfRegAlias<B9>;
-def Q10 : AArch64Reg<10, "q10", [D10], ["v10", ""]>, DwarfRegAlias<B10>;
-def Q11 : AArch64Reg<11, "q11", [D11], ["v11", ""]>, DwarfRegAlias<B11>;
-def Q12 : AArch64Reg<12, "q12", [D12], ["v12", ""]>, DwarfRegAlias<B12>;
-def Q13 : AArch64Reg<13, "q13", [D13], ["v13", ""]>, DwarfRegAlias<B13>;
-def Q14 : AArch64Reg<14, "q14", [D14], ["v14", ""]>, DwarfRegAlias<B14>;
-def Q15 : AArch64Reg<15, "q15", [D15], ["v15", ""]>, DwarfRegAlias<B15>;
-def Q16 : AArch64Reg<16, "q16", [D16], ["v16", ""]>, DwarfRegAlias<B16>;
-def Q17 : AArch64Reg<17, "q17", [D17], ["v17", ""]>, DwarfRegAlias<B17>;
-def Q18 : AArch64Reg<18, "q18", [D18], ["v18", ""]>, DwarfRegAlias<B18>;
-def Q19 : AArch64Reg<19, "q19", [D19], ["v19", ""]>, DwarfRegAlias<B19>;
-def Q20 : AArch64Reg<20, "q20", [D20], ["v20", ""]>, DwarfRegAlias<B20>;
-def Q21 : AArch64Reg<21, "q21", [D21], ["v21", ""]>, DwarfRegAlias<B21>;
-def Q22 : AArch64Reg<22, "q22", [D22], ["v22", ""]>, DwarfRegAlias<B22>;
-def Q23 : AArch64Reg<23, "q23", [D23], ["v23", ""]>, DwarfRegAlias<B23>;
-def Q24 : AArch64Reg<24, "q24", [D24], ["v24", ""]>, DwarfRegAlias<B24>;
-def Q25 : AArch64Reg<25, "q25", [D25], ["v25", ""]>, DwarfRegAlias<B25>;
-def Q26 : AArch64Reg<26, "q26", [D26], ["v26", ""]>, DwarfRegAlias<B26>;
-def Q27 : AArch64Reg<27, "q27", [D27], ["v27", ""]>, DwarfRegAlias<B27>;
-def Q28 : AArch64Reg<28, "q28", [D28], ["v28", ""]>, DwarfRegAlias<B28>;
-def Q29 : AArch64Reg<29, "q29", [D29], ["v29", ""]>, DwarfRegAlias<B29>;
-def Q30 : AArch64Reg<30, "q30", [D30], ["v30", ""]>, DwarfRegAlias<B30>;
-def Q31 : AArch64Reg<31, "q31", [D31], ["v31", ""]>, DwarfRegAlias<B31>;
+let SubRegIndices = [bsub, bsub_hi] in {
+def H0 : AArch64Reg<0, "h0", [B0, B0_HI]>, DwarfRegAlias<B0>;
+def H1 : AArch64Reg<1, "h1", [B1, B1_HI]>, DwarfRegAlias<B1>;
+def H2 : AArch64Reg<2, "h2", [B2, B2_HI]>, DwarfRegAlias<B2>;
+def H3 : AArch64Reg<3, "h3", [B3, B3_HI]>, DwarfRegAlias<B3>;
+def H4 : AArch64Reg<4, "h4", [B4, B4_HI]>, DwarfRegAlias<B4>;
+def H5 : AArch64Reg<5, "h5", [B5, B5_HI]>, DwarfRegAlias<B5>;
+def H6 : AArch64Reg<6, "h6", [B6, B6_HI]>, DwarfRegAlias<B6>;
+def H7 : AArch64Reg<7, "h7", [B7, B7_HI]>, DwarfRegAlias<B7>;
+def H8 : AArch64Reg<8, "h8", [B8, B8_HI]>, DwarfRegAlias<B8>;
+def H9 : AArch64Reg<9, "h9", [B9, B9_HI]>, DwarfRegAlias<B9>;
+def H10 : AArch64Reg<10, "h10", [B10, B10_HI]>, DwarfRegAlias<B10>;
+def H11 : AArch64Reg<11, "h11", [B11, B11_HI]>, DwarfRegAlias<B11>;
+def H12 : AArch64Reg<12, "h12", [B12, B12_HI]>, DwarfRegAlias<B12>;
+def H13 : AArch64Reg<13, "h13", [B13, B13_HI]>, DwarfRegAlias<B13>;
+def H14 : AArch64Reg<14, "h14", [B14, B14_HI]>, DwarfRegAlias<B14>;
+def H15 : AArch64Reg<15, "h15", [B15, B15_HI]>, DwarfRegAlias<B15>;
+def H16 : AArch64Reg<16, "h16", [B16, B16_HI]>, DwarfRegAlias<B16>;
+def H17 : AArch64Reg<17, "h17", [B17, B17_HI]>, DwarfRegAlias<B17>;
+def H18 : AArch64Reg<18, "h18", [B18, B18_HI]>, DwarfRegAlias<B18>;
+def H19 : AArch64Reg<19, "h19", [B19, B19_HI]>, DwarfRegAlias<B19>;
+def H20 : AArch64Reg<20, "h20", [B20, B20_HI]>, DwarfRegAlias<B20>;
+def H21 : AArch64Reg<21, "h21", [B21, B21_HI]>, DwarfRegAlias<B21>;
+def H22 : AArch64Reg<22, "h22", [B22, B22_HI]>, DwarfRegAlias<B22>;
+def H23 : AArch64Reg<23, "h23", [B23, B23_HI]>, DwarfRegAlias<B23>;
+def H24 : AArch64Reg<24, "h24", [B24, B24_HI]>, DwarfRegAlias<B24>;
+def H25 : AArch64Reg<25, "h25", [B25, B25_HI]>, DwarfRegAlias<B25>;
+def H26 : AArch64Reg<26, "h26", [B26, B26_HI]>, DwarfRegAlias<B26>;
+def H27 : AArch64Reg<27, "h27", [B27, B27_HI]>, DwarfRegAlias<B27>;
+def H28 : AArch64Reg<28, "h28", [B28, B28_HI]>, DwarfRegAlias<B28>;
+def H29 : AArch64Reg<29, "h29", [B29, B29_HI]>, DwarfRegAlias<B29>;
+def H30 : AArch64Reg<30, "h30", [B30, B30_HI]>, DwarfRegAlias<B30>;
+def H31 : AArch64Reg<31, "h31", [B31, B31_HI]>, DwarfRegAlias<B31>;
+}
+
+let SubRegIndices = [hsub, hsub_hi] in {
+def S0 : AArch64Reg<0, "s0", [H0, H0_HI]>, DwarfRegAlias<B0>;
+def S1 : AArch64Reg<1, "s1", [H1, H1_HI]>, DwarfRegAlias<B1>;
+def S2 : AArch64Reg<2, "s2", [H2, H2_HI]>, DwarfRegAlias<B2>;
+def S3 : AArch64Reg<3, "s3", [H3, H3_HI]>, DwarfRegAlias<B3>;
+def S4 : AArch64Reg<4, "s4", [H4, H4_HI]>, DwarfRegAlias<B4>;
+def S5 : AArch64Reg<5, "s5", [H5, H5_HI]>, DwarfRegAlias<B5>;
+def S6 : AArch64Reg<6, "s6", [H6, H6_HI]>, DwarfRegAlias<B6>;
+def S7 : AArch64Reg<7, "s7", [H7, H7_HI]>, DwarfRegAlias<B7>;
+def S8 : AArch64Reg<8, "s8", [H8, H8_HI]>, DwarfRegAlias<B8>;
+def S9 : AArch64Reg<9, "s9", [H9, H9_HI]>, DwarfRegAlias<B9>;
+def S10 : AArch64Reg<10, "s10", [H10, H10_HI]>, DwarfRegAlias<B10>;
+def S11 : AArch64Reg<11, "s11", [H11, H11_HI]>, DwarfRegAlias<B11>;
+def S12 : AArch64Reg<12, "s12", [H12, H12_HI]>, DwarfRegAlias<B12>;
+def S13 : AArch64Reg<13, "s13", [H13, H13_HI]>, DwarfRegAlias<B13>;
+def S14 : AArch64Reg<14, "s14", [H14, H14_HI]>, DwarfRegAlias<B14>;
+def S15 : AArch64Reg<15, "s15", [H15, H15_HI]>, DwarfRegAlias<B15>;
+def S16 : AArch64Reg<16, "s16", [H16, H16_HI]>, DwarfRegAlias<B16>;
+def S17 : AArch64Reg<17, "s17", [H17, H17_HI]>, DwarfRegAlias<B17>;
+def S18 : AArch64Reg<18, "s18", [H18, H18_HI]>, DwarfRegAlias<B18>;
+def S19 : AArch64Reg<19, "s19", [H19, H19_HI]>, DwarfRegAlias<B19>;
+def S20 : AArch64Reg<20, "s20", [H20, H20_HI]>, DwarfRegAlias<B20>;
+def S21 : AArch64Reg<21, "s21", [H21, H21_HI]>, DwarfRegAlias<B21>;
+def S22 : AArch64Reg<22, "s22", [H22, H22_HI]>, DwarfRegAlias<B22>;
+def S23 : AArch64Reg<23, "s23", [H23, H23_HI]>, DwarfRegAlias<B23>;
+def S24 : AArch64Reg<24, "s24", [H24, H24_HI]>, DwarfRegAlias<B24>;
+def S25 : AArch64Reg<25, "s25", [H25, H25_HI]>, DwarfRegAlias<B25>;
+def S26 : AArch64Reg<26, "s26", [H26, H26_HI]>, DwarfRegAlias<B26>;
+def S27 : AArch64Reg<27, "s27", [H27, H27_HI]>, DwarfRegAlias<B27>;
+def S28 : AArch64Reg<28, "s28", [H28, H28_HI]>, DwarfRegAlias<B28>;
+def S29 : AArch64Reg<29, "s29", [H29, H29_HI]>, DwarfRegAlias<B29>;
+def S30 : AArch64Reg<30, "s30", [H30, H30_HI]>, DwarfRegAlias<B30>;
+def S31 : AArch64Reg<31, "s31", [H31, H31_HI]>, DwarfRegAlias<B31>;
+}
+
+let SubRegIndices = [ssub, ssub_hi], RegAltNameIndices = [vreg, vlist1] in {
+def D0 : AArch64Reg<0, "d0", [S0, S0_HI], ["v0", ""]>, DwarfRegAlias<B0>;
+def D1 : AArch64Reg<1, "d1", [S1, S1_HI], ["v1", ""]>, DwarfRegAlias<B1>;
+def D2 : AArch64Reg<2, "d2", [S2, S2_HI], ["v2", ""]>, DwarfRegAlias<B2>;
+def D3 : AArch64Reg<3, "d3", [S3, S3_HI], ["v3", ""]>, DwarfRegAlias<B3>;
+def D4 : AArch64Reg<4, "d4", [S4, S4_HI], ["v4", ""]>, DwarfRegAlias<B4>;
+def D5 : AArch64Reg<5, "d5", [S5, S5_HI], ["v5", ""]>, DwarfRegAlias<B5>;
+def D6 : AArch64Reg<6, "d6", [S6, S6_HI], ["v6", ""]>, DwarfRegAlias<B6>;
+def D7 : AArch64Reg<7, "d7", [S7, S7_HI], ["v7", ""]>, DwarfRegAlias<B7>;
+def D8 : AArch64Reg<8, "d8", [S8, S8_HI], ["v8", ""]>, DwarfRegAlias<B8>;
+def D9 : AArch64Reg<9, "d9", [S9, S9_HI], ["v9", ""]>, DwarfRegAlias<B9>;
+def D10 : AArch64Reg<10, "d10", [S10, S10_HI], ["v10", ""]>, DwarfRegAlias<B10>;
+def D11 : AArch64Reg<11, "d11", [S11, S11_HI], ["v11", ""]>, DwarfRegAlias<B11>;
+def D12 : AArch64Reg<12, "d12", [S12, S12_HI], ["v12", ""]>, DwarfRegAlias<B12>;
+def D13 : AArch64Reg<13, "d13", [S13, S13_HI], ["v13", ""]>, DwarfRegAlias<B13>;
+def D14 : AArch64Reg<14, "d14", [S14, S14_HI], ["v14", ""]>, DwarfRegAlias<B14>;
+def D15 : AArch64Reg<15, "d15", [S15, S15_HI], ["v15", ""]>, DwarfRegAlias<B15>;
+def D16 : AArch64Reg<16, "d16", [S16, S16_HI], ["v16", ""]>, DwarfRegAlias<B16>;
+def D17 : AArch64Reg<17, "d17", [S17, S17_HI], ["v17", ""]>, DwarfRegAlias<B17>;
+def D18 : AArch64Reg<18, "d18", [S18, S18_HI], ["v18", ""]>, DwarfRegAlias<B18>;
+def D19 : AArch64Reg<19, "d19", [S19, S19_HI], ["v19", ""]>, DwarfRegAlias<B19>;
+def D20 : AArch64Reg<20, "d20", [S20, S20_HI], ["v20", ""]>, DwarfRegAlias<B20>;
+def D21 : AArch64Reg<21, "d21", [S21, S21_HI], ["v21", ""]>, DwarfRegAlias<B21>;
+def D22 : AArch64Reg<22, "d22", [S22, S22_HI], ["v22", ""]>, DwarfRegAlias<B22>;
+def D23 : AArch64Reg<23, "d23", [S23, S23_HI], ["v23", ""]>, DwarfRegAlias<B23>;
+def D24 : AArch64Reg<24, "d24", [S24, S24_HI], ["v24", ""]>, DwarfRegAlias<B24>;
+def D25 : AArch64Reg<25, "d25", [S25, S25_HI], ["v25", ""]>, DwarfRegAlias<B25>;
+def D26 : AArch64Reg<26, "d26", [S26, S26_HI], ["v26", ""]>, DwarfRegAlias<B26>;
+def D27 : AArch64Reg<27, "d27", [S27, S27_HI], ["v27", ""]>, DwarfRegAlias<B27>;
+def D28 : AArch64Reg<28, "d28", [S28, S28_HI], ["v28", ""]>, DwarfRegAlias<B28>;
+def D29 : AArch64Reg<29, "d29", [S29, S29_HI], ["v29", ""]>, DwarfRegAlias<B29>;
+def D30 : AArch64Reg<30, "d30", [S30, S30_HI], ["v30", ""]>, DwarfRegAlias<B30>;
+def D31 : AArch64Reg<31, "d31", [S31, S31_HI], ["v31", ""]>, DwarfRegAlias<B31>;
+}
+
+let SubRegIndices = [dsub, dsub_hi], RegAltNameIndices = [vreg, vlist1] in {
+def Q0 : AArch64Reg<0, "q0", [D0, D0_HI], ["v0", ""]>, DwarfRegAlias<B0>;
+def Q1 : AArch64Reg<1, "q1", [D1, D1_HI], ["v1", ""]>, DwarfRegAlias<B1>;
+def Q2 : AArch64Reg<2, "q2", [D2, D2_HI], ["v2", ""]>, DwarfRegAlias<B2>;
+def Q3 : AArch64Reg<3, "q3", [D3, D3_HI], ["v3", ""]>, DwarfRegAlias<B3>;
+def Q4 : AArch64Reg<4, "q4", [D4, D4_HI], ["v4", ""]>, DwarfRegAlias<B4>;
+def Q5 : AArch64Reg<5, "q5", [D5, D5_HI], ["v5", ""]>, DwarfRegAlias<B5>;
+def Q6 : AArch64Reg<6, "q6", [D6, D6_HI], ["v6", ""]>, DwarfRegAlias<B6>;
+def Q7 : AArch64Reg<7, "q7", [D7, D7_HI], ["v7", ""]>, DwarfRegAlias<B7>;
+def Q8 : AArch64Reg<8, "q8", [D8, D8_HI], ["v8", ""]>, DwarfRegAlias<B8>;
+def Q9 : AArch64Reg<9, "q9", [D9, D9_HI], ["v9", ""]>, DwarfRegAlias<B9>;
+def Q10 : AArch64Reg<10, "q10", [D10, D10_HI], ["v10", ""]>, DwarfRegAlias<B10>;
+def Q11 : AArch64Reg<11, "q11", [D11, D11_HI], ["v11", ""]>, DwarfRegAlias<B11>;
+def Q12 : AArch64Reg<12, "q12", [D12, D12_HI], ["v12", ""]>, DwarfRegAlias<B12>;
+def Q13 : AArch64Reg<13, "q13", [D13, D13_HI], ["v13", ""]>, DwarfRegAlias<B13>;
+def Q14 : AArch64Reg<14, "q14", [D14, D14_HI], ["v14", ""]>, DwarfRegAlias<B14>;
+def Q15 : AArch64Reg<15, "q15", [D15, D15_HI], ["v15", ""]>, DwarfRegAlias<B15>;
+def Q16 : AArch64Reg<16, "q16", [D16, D16_HI], ["v16", ""]>, DwarfRegAlias<B16>;
+def Q17 : AArch64Reg<17, "q17", [D17, D17_HI], ["v17", ""]>, DwarfRegAlias<B17>;
+def Q18 : AArch64Reg<18, "q18", [D18, D18_HI], ["v18", ""]>, DwarfRegAlias<B18>;
+def Q19 : AArch64Reg<19, "q19", [D19, D19_HI], ["v19", ""]>, DwarfRegAlias<B19>;
+def Q20 : AArch64Reg<20, "q20", [D20, D20_HI], ["v20", ""]>, DwarfRegAlias<B20>;
+def Q21 : AArch64Reg<21, "q21", [D21, D21_HI], ["v21", ""]>, DwarfRegAlias<B21>;
+def Q22 : AArch64Reg<22, "q22", [D22, D22_HI], ["v22", ""]>, DwarfRegAlias<B22>;
+def Q23 : AArch64Reg<23, "q23", [D23, D23_HI], ["v23", ""]>, DwarfRegAlias<B23>;
+def Q24 : AArch64Reg<24, "q24", [D24, D24_HI], ["v24", ""]>, DwarfRegAlias<B24>;
+def Q25 : AArch64Reg<25, "q25", [D25, D25_HI], ["v25", ""]>, DwarfRegAlias<B25>;
+def Q26 : AArch64Reg<26, "q26", [D26, D26_HI], ["v26", ""]>, DwarfRegAlias<B26>;
+def Q27 : AArch64Reg<27, "q27", [D27, D27_HI], ["v27", ""]>, DwarfRegAlias<B27>;
+def Q28 : AArch64Reg<28, "q28", [D28, D28_HI], ["v28", ""]>, DwarfRegAlias<B28>;
+def Q29 : AArch64Reg<29, "q29", [D29, D29_HI], ["v29", ""]>, DwarfRegAlias<B29>;
+def Q30 : AArch64Reg<30, "q30", [D30, D30_HI], ["v30", ""]>, DwarfRegAlias<B30>;
+def Q31 : AArch64Reg<31, "q31", [D31, D31_HI], ["v31", ""]>, DwarfRegAlias<B31>;
}
def FPR8 : RegisterClass<"AArch64", [i8], 8, (sequence "B%u", 0, 31)> {
@@ -868,39 +888,39 @@ let SubRegIndices = [psub] in {
}
// SVE variable-size vector registers
-let SubRegIndices = [zsub] in {
-def Z0 : AArch64Reg<0, "z0", [Q0]>, DwarfRegNum<[96]>;
-def Z1 : AArch64Reg<1, "z1", [Q1]>, DwarfRegNum<[97]>;
-def Z2 : AArch64Reg<2, "z2", [Q2]>, DwarfRegNum<[98]>;
-def Z3 : AArch64Reg<3, "z3", [Q3]>, DwarfRegNum<[99]>;
-def Z4 : AArch64Reg<4, "z4", [Q4]>, DwarfRegNum<[100]>;
-def Z5 : AArch64Reg<5, "z5", [Q5]>, DwarfRegNum<[101]>;
-def Z6 : AArch64Reg<6, "z6", [Q6]>, DwarfRegNum<[102]>;
-def Z7 : AArch64Reg<7, "z7", [Q7]>, DwarfRegNum<[103]>;
-def Z8 : AArch64Reg<8, "z8", [Q8]>, DwarfRegNum<[104]>;
-def Z9 : AArch64Reg<9, "z9", [Q9]>, DwarfRegNum<[105]>;
-def Z10 : AArch64Reg<10, "z10", [Q10]>, DwarfRegNum<[106]>;
-def Z11 : AArch64Reg<11, "z11", [Q11]>, DwarfRegNum<[107]>;
-def Z12 : AArch64Reg<12, "z12", [Q12]>, DwarfRegNum<[108]>;
-def Z13 : AArch64Reg<13, "z13", [Q13]>, DwarfRegNum<[109]>;
-def Z14 : AArch64Reg<14, "z14", [Q14]>, DwarfRegNum<[110]>;
-def Z15 : AArch64Reg<15, "z15", [Q15]>, DwarfRegNum<[111]>;
-def Z16 : AArch64Reg<16, "z16", [Q16]>, DwarfRegNum<[112]>;
-def Z17 : AArch64Reg<17, "z17", [Q17]>, DwarfRegNum<[113]>;
-def Z18 : AArch64Reg<18, "z18", [Q18]>, DwarfRegNum<[114]>;
-def Z19 : AArch64Reg<19, "z19", [Q19]>, DwarfRegNum<[115]>;
-def Z20 : AArch64Reg<20, "z20", [Q20]>, DwarfRegNum<[116]>;
-def Z21 : AArch64Reg<21, "z21", [Q21]>, DwarfRegNum<[117]>;
-def Z22 : AArch64Reg<22, "z22", [Q22]>, DwarfRegNum<[118]>;
-def Z23 : AArch64Reg<23, "z23", [Q23]>, DwarfRegNum<[119]>;
-def Z24 : AArch64Reg<24, "z24", [Q24]>, DwarfRegNum<[120]>;
-def Z25 : AArch64Reg<25, "z25", [Q25]>, DwarfRegNum<[121]>;
-def Z26 : AArch64Reg<26, "z26", [Q26]>, DwarfRegNum<[122]>;
-def Z27 : AArch64Reg<27, "z27", [Q27]>, DwarfRegNum<[123]>;
-def Z28 : AArch64Reg<28, "z28", [Q28]>, DwarfRegNum<[124]>;
-def Z29 : AArch64Reg<29, "z29", [Q29]>, DwarfRegNum<[125]>;
-def Z30 : AArch64Reg<30, "z30", [Q30]>, DwarfRegNum<[126]>;
-def Z31 : AArch64Reg<31, "z31", [Q31]>, DwarfRegNum<[127]>;
+let SubRegIndices = [zsub, zsub_hi] in {
+def Z0 : AArch64Reg<0, "z0", [Q0, Q0_HI]>, DwarfRegNum<[96]>;
+def Z1 : AArch64Reg<1, "z1", [Q1, Q1_HI]>, DwarfRegNum<[97]>;
+def Z2 : AArch64Reg<2, "z2", [Q2, Q2_HI]>, DwarfRegNum<[98]>;
+def Z3 : AArch64Reg<3, "z3", [Q3, Q3_HI]>, DwarfRegNum<[99]>;
+def Z4 : AArch64Reg<4, "z4", [Q4, Q4_HI]>, DwarfRegNum<[100]>;
+def Z5 : AArch64Reg<5, "z5", [Q5, Q5_HI]>, DwarfRegNum<[101]>;
+def Z6 : AArch64Reg<6, "z6", [Q6, Q6_HI]>, DwarfRegNum<[102]>;
+def Z7 : AArch64Reg<7, "z7", [Q7, Q7_HI]>, DwarfRegNum<[103]>;
+def Z8 : AArch64Reg<8, "z8", [Q8, Q8_HI]>, DwarfRegNum<[104]>;
+def Z9 : AArch64Reg<9, "z9", [Q9, Q9_HI]>, DwarfRegNum<[105]>;
+def Z10 : AArch64Reg<10, "z10", [Q10, Q10_HI]>, DwarfRegNum<[106]>;
+def Z11 : AArch64Reg<11, "z11", [Q11, Q11_HI]>, DwarfRegNum<[107]>;
+def Z12 : AArch64Reg<12, "z12", [Q12, Q12_HI]>, DwarfRegNum<[108]>;
+def Z13 : AArch64Reg<13, "z13", [Q13, Q13_HI]>, DwarfRegNum<[109]>;
+def Z14 : AArch64Reg<14, "z14", [Q14, Q14_HI]>, DwarfRegNum<[110]>;
+def Z15 : AArch64Reg<15, "z15", [Q15, Q15_HI]>, DwarfRegNum<[111]>;
+def Z16 : AArch64Reg<16, "z16", [Q16, Q16_HI]>, DwarfRegNum<[112]>;
+def Z17 : AArch64Reg<17, "z17", [Q17, Q17_HI]>, DwarfRegNum<[113]>;
+def Z18 : AArch64Reg<18, "z18", [Q18, Q18_HI]>, DwarfRegNum<[114]>;
+def Z19 : AArch64Reg<19, "z19", [Q19, Q19_HI]>, DwarfRegNum<[115]>;
+def Z20 : AArch64Reg<20, "z20", [Q20, Q20_HI]>, DwarfRegNum<[116]>;
+def Z21 : AArch64Reg<21, "z21", [Q21, Q21_HI]>, DwarfRegNum<[117]>;
+def Z22 : AArch64Reg<22, "z22", [Q22, Q22_HI]>, DwarfRegNum<[118]>;
+def Z23 : AArch64Reg<23, "z23", [Q23, Q23_HI]>, DwarfRegNum<[119]>;
+def Z24 : AArch64Reg<24, "z24", [Q24, Q24_HI]>, DwarfRegNum<[120]>;
+def Z25 : AArch64Reg<25, "z25", [Q25, Q25_HI]>, DwarfRegNum<[121]>;
+def Z26 : AArch64Reg<26, "z26", [Q26, Q26_HI]>, DwarfRegNum<[122]>;
+def Z27 : AArch64Reg<27, "z27", [Q27, Q27_HI]>, DwarfRegNum<[123]>;
+def Z28 : AArch64Reg<28, "z28", [Q28, Q28_HI]>, DwarfRegNum<[124]>;
+def Z29 : AArch64Reg<29, "z29", [Q29, Q29_HI]>, DwarfRegNum<[125]>;
+def Z30 : AArch64Reg<30, "z30", [Q30, Q30_HI]>, DwarfRegNum<[126]>;
+def Z31 : AArch64Reg<31, "z31", [Q31, Q31_HI]>, DwarfRegNum<[127]>;
}
// Enum describing the element size for destructive
@@ -1945,6 +1965,15 @@ def svcr_op : Operand<i32>, TImmLeaf<i32, [{
}];
}
+let isAllocatable = 0, GeneratePressureSet = 0 in {
+ def W_HI_DummyRC : RegisterClass<"AArch64", [untyped], 0, (add (sequence "W%u_HI", 0, 30), WZR_HI, WSP_HI)>;
+ def B_HI_DummyRC : RegisterClass<"AArch64", [untyped], 0, (sequence "B%u_HI", 0, 31)>;
+ def H_HI_DummyRC : RegisterClass<"AArch64", [untyped], 0, (sequence "H%u_HI", 0, 31)>;
+ def S_HI_DummyRC : RegisterClass<"AArch64", [untyped], 0, (sequence "S%u_HI", 0, 31)>;
+ def D_HI_DummyRC : RegisterClass<"AArch64", [untyped], 0, (sequence "D%u_HI", 0, 31)>;
+ def Q_HI_DummyRC : RegisterClass<"AArch64", [untyped], 0, (sequence "Q%u_HI", 0, 31)>;
+}
+
//===----------------------------------------------------------------------===//
// Register categories.
//
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
index f1d1b691fe1aa5..216f94b2b51e3f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
@@ -57,11 +57,11 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: inlineasm_virt_reg_output
- ; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 2490378 /* regdef:GPR32common */, def %0
+ ; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 2883594 /* regdef:GPR32common */, def %0
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %0
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
- INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 2490378 /* regdef:GPR32common */, def %0:gpr32common
+ INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 2883594 /* regdef:GPR32common */, def %0:gpr32common
%1:_(s32) = COPY %0
$w0 = COPY %1(s32)
RET_ReallyLR implicit $w0
@@ -75,12 +75,12 @@ tracksRegLiveness: true
body: |
bb.1:
; CHECK-LABEL: name: inlineasm_virt_mixed_types
- ; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 2490378 /* regdef:GPR32common */, def %0, 3342346 /* regdef:FPR64 */, def %1
+ ; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 2883594 /* regdef:GPR32common */, def %0, 3735562 /* regdef:FPR64 */, def %1
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s64) = COPY %1
; CHECK-NEXT: $d0 = COPY [[COPY1]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $d0
- INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 2490378 /* regdef:GPR32common */, def %0:gpr32common, 3342346 /* regdef:FPR64 */, def %1:fpr64
+ INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 2883594 /* regdef:GPR32common */, def %0:gpr32common, 3735562 /* regdef:FPR64 */, def %1:fpr64
%3:_(s32) = COPY %0
%4:_(s64) = COPY %1
$d0 = COPY %4(s64)
diff --git a/llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll b/llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
index ff66206228a4aa..0e8465e7419936 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
@@ -13,7 +13,7 @@ define <vscale x 16 x i8> @test_svadd_i8(<vscale x 16 x i8> %Zn, <vscale x 16 x
; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr_3b = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"add $0.b, $1.b, $2.b", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %2, 5767177 /* reguse:ZPR */, [[COPY2]], 6357001 /* reguse:ZPR_3b */, [[COPY3]]
+ ; CHECK-NEXT: INLINEASM &"add $0.b, $1.b, $2.b", 0 /* attdialect */, {{[0-9]+}} /* regdef:ZPR */, def %2, {{[0-9]+}} /* reguse:ZPR */, [[COPY2]], {{[0-9]+}} /* reguse:ZPR_3b */, [[COPY3]]
; CHECK-NEXT: $z0 = COPY %2
; CHECK-NEXT: RET_ReallyLR implicit $z0
%1 = tail call <vscale x 16 x i8> asm "add $0.b, $1.b, $2.b", "=w,w,y"(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm)
@@ -29,7 +29,7 @@ define <vscale x 2 x i64> @test_svsub_i64(<vscale x 2 x i64> %Zn, <vscale x 2 x
; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr_4b = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"sub $0.d, $1.d, $2.d", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %2, 5767177 /* reguse:ZPR */, [[COPY2]], 6029321 /* reguse:ZPR_4b */, [[COPY3]]
+ ; CHECK-NEXT: INLINEASM &"sub $0.d, $1.d, $2.d", 0 /* attdialect */, {{[0-9]+}} /* regdef:ZPR */, def %2, {{[0-9]+}} /* reguse:ZPR */, [[COPY2]], {{[0-9]+}} /* reguse:ZPR_4b */, [[COPY3]]
; CHECK-NEXT: $z0 = COPY %2
; CHECK-NEXT: RET_ReallyLR implicit $z0
%1 = tail call <vscale x 2 x i64> asm "sub $0.d, $1.d, $2.d", "=w,w,x"(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm)
@@ -45,7 +45,7 @@ define <vscale x 8 x half> @test_svfmul_f16(<vscale x 8 x half> %Zn, <vscale x 8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr_3b = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"fmul $0.h, $1.h, $2.h", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %2, 5767177 /* reguse:ZPR */, [[COPY2]], 6357001 /* reguse:ZPR_3b */, [[COPY3]]
+ ; CHECK-NEXT: INLINEASM &"fmul $0.h, $1.h, $2.h", 0 /* attdialect */, {{[0-9]+}} /* regdef:ZPR */, def %2, {{[0-9]+}} /* reguse:ZPR */, [[COPY2]], {{[0-9]+}} /* reguse:ZPR_3b */, [[COPY3]]
; CHECK-NEXT: $z0 = COPY %2
; CHECK-NEXT: RET_ReallyLR implicit $z0
%1 = tail call <vscale x 8 x half> asm "fmul $0.h, $1.h, $2.h", "=w,w,y"(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
@@ -61,7 +61,7 @@ define <vscale x 4 x float> @test_svfmul_f(<vscale x 4 x float> %Zn, <vscale x 4
; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr_4b = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"fmul $0.s, $1.s, $2.s", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %2, 5767177 /* reguse:ZPR */, [[COPY2]], 6029321 /* reguse:ZPR_4b */, [[COPY3]]
+ ; CHECK-NEXT: INLINEASM &"fmul $0.s, $1.s, $2.s", 0 /* attdialect */, {{[0-9]+}} /* regdef:ZPR */, def %2, {{[0-9]+}} /* reguse:ZPR */, [[COPY2]], {{[0-9]+}} /* reguse:ZPR_4b */, [[COPY3]]
; CHECK-NEXT: $z0 = COPY %2
; CHECK-NEXT: RET_ReallyLR implicit $z0
%1 = tail call <vscale x 4 x float> asm "fmul $0.s, $1.s, $2.s", "=w,w,x"(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm)
@@ -79,7 +79,7 @@ define <vscale x 8 x half> @test_svfadd_f16(<vscale x 16 x i1> %Pg, <vscale x 8
; CHECK-NEXT: [[COPY3:%[0-9]+]]:ppr_3b = COPY [[COPY2]]
; CHECK-NEXT: [[COPY4:%[0-9]+]]:zpr = COPY [[COPY1]]
; CHECK-NEXT: [[COPY5:%[0-9]+]]:zpr = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"fadd $0.h, $1/m, $2.h, $3.h", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %3, 720905 /* reguse:PPR_3b */, [[COPY3]], 5767177 /* reguse:ZPR */, [[COPY4]], 5767177 /* reguse:ZPR */, [[COPY5]]
+ ; CHECK-NEXT: INLINEASM &"fadd $0.h, $1/m, $2.h, $3.h", 0 /* attdialect */, {{[0-9]+}} /* regdef:ZPR */, def %3, {{[0-9]+}} /* reguse:PPR_3b */, [[COPY3]], {{[0-9]+}} /* reguse:ZPR */, [[COPY4]], {{[0-9]+}} /* reguse:ZPR */, [[COPY5]]
; CHECK-NEXT: $z0 = COPY %3
; CHECK-NEXT: RET_ReallyLR implicit $z0
%1 = tail call <vscale x 8 x half> asm "fadd $0.h, $1/m, $2.h, $3.h", "=w, at 3Upl,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
@@ -95,7 +95,7 @@ define <vscale x 4 x i32> @test_incp(<vscale x 16 x i1> %Pg, <vscale x 4 x i32>
; CHECK-NEXT: [[COPY1:%[0-9]+]]:ppr = COPY $p0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:ppr = COPY [[COPY1]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"incp $0.s, $1", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %2, 458761 /* reguse:PPR */, [[COPY2]], 2147483657 /* reguse tiedto:$0 */, [[COPY3]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &"incp $0.s, $1", 0 /* attdialect */, {{[0-9]+}} /* regdef:ZPR */, def %2, {{[0-9]+}} /* reguse:PPR */, [[COPY2]], {{[0-9]+}} /* reguse tiedto:$0 */, [[COPY3]](tied-def 3)
; CHECK-NEXT: $z0 = COPY %2
; CHECK-NEXT: RET_ReallyLR implicit $z0
%1 = tail call <vscale x 4 x i32> asm "incp $0.s, $1", "=w, at 3Upa,0"(<vscale x 16 x i1> %Pg, <vscale x 4 x i32> %Zn)
@@ -113,7 +113,7 @@ define <vscale x 8 x half> @test_svfadd_f16_Uph_constraint(<vscale x 16 x i1> %P
; CHECK-NEXT: [[COPY3:%[0-9]+]]:ppr_p8to15 = COPY [[COPY2]]
; CHECK-NEXT: [[COPY4:%[0-9]+]]:zpr = COPY [[COPY1]]
; CHECK-NEXT: [[COPY5:%[0-9]+]]:zpr = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"fadd $0.h, $1/m, $2.h, $3.h", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %3, 786441 /* reguse:PPR_p8to15 */, [[COPY3]], 5767177 /* reguse:ZPR */, [[COPY4]], 5767177 /* reguse:ZPR */, [[COPY5]]
+ ; CHECK-NEXT: INLINEASM &"fadd $0.h, $1/m, $2.h, $3.h", 0 /* attdialect */, {{[0-9]+}} /* regdef:ZPR */, def %3, {{[0-9]+}} /* reguse:PPR_p8to15 */, [[COPY3]], {{[0-9]+}} /* reguse:ZPR */, [[COPY4]], {{[0-9]+}} /* reguse:ZPR */, [[COPY5]]
; CHECK-NEXT: $z0 = COPY %3
; CHECK-NEXT: RET_ReallyLR implicit $z0
%1 = tail call <vscale x 8 x half> asm "fadd $0.h, $1/m, $2.h, $3.h", "=w, at 3Uph,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
@@ -129,7 +129,7 @@ define void @explicit_p0(ptr %p) {
; CHECK-NEXT: [[PTRUE_B:%[0-9]+]]:ppr = PTRUE_B 31, implicit $vg
; CHECK-NEXT: $p0 = COPY [[PTRUE_B]]
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"ld4w { z0.s, z1.s, z2.s, z3.s }, $1/z, [$0]", 1 /* sideeffect attdialect */, 3538954 /* regdef:GPR64common */, def %1, 9 /* reguse */, $p0, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &"ld4w { z0.s, z1.s, z2.s, z3.s }, $1/z, [$0]", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:GPR64common */, def %1, 9 /* reguse */, $p0, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3)
; CHECK-NEXT: RET_ReallyLR
%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.b8(i32 31)
%2 = tail call i64 asm sideeffect "ld4w { z0.s, z1.s, z2.s, z3.s }, $1/z, [$0]", "=r,{p0},0"(<vscale x 16 x i1> %1, ptr %p)
@@ -145,7 +145,7 @@ define void @explicit_p8_invalid(ptr %p) {
; CHECK-NEXT: [[PTRUE_B:%[0-9]+]]:ppr = PTRUE_B 31, implicit $vg
; CHECK-NEXT: $p8 = COPY [[PTRUE_B]]
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"ld4w { z0.s, z1.s, z2.s, z3.s }, $1/z, [$0]", 1 /* sideeffect attdialect */, 3538954 /* regdef:GPR64common */, def %1, 9 /* reguse */, $p8, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &"ld4w { z0.s, z1.s, z2.s, z3.s }, $1/z, [$0]", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:GPR64common */, def %1, 9 /* reguse */, $p8, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3)
; CHECK-NEXT: RET_ReallyLR
%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.b8(i32 31)
%2 = tail call i64 asm sideeffect "ld4w { z0.s, z1.s, z2.s, z3.s }, $1/z, [$0]", "=r,{p8},0"(<vscale x 16 x i1> %1, ptr %p)
@@ -161,7 +161,7 @@ define void @explicit_pn8(ptr %p) {
; CHECK-NEXT: [[PTRUE_C_B:%[0-9]+]]:pnr_p8to15 = PTRUE_C_B implicit $vg
; CHECK-NEXT: $pn8 = COPY [[PTRUE_C_B]]
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"ld1w { z0.s, z4.s, z8.s, z12.s }, $1/z, [$0]", 1 /* sideeffect attdialect */, 3538954 /* regdef:GPR64common */, def %1, 9 /* reguse */, $pn8, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &"ld1w { z0.s, z4.s, z8.s, z12.s }, $1/z, [$0]", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:GPR64common */, def %1, 9 /* reguse */, $pn8, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3)
; CHECK-NEXT: RET_ReallyLR
%1 = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c8()
%2 = tail call i64 asm sideeffect "ld1w { z0.s, z4.s, z8.s, z12.s }, $1/z, [$0]", "=r,{pn8},0"(target("aarch64.svcount") %1, ptr %p)
@@ -177,7 +177,7 @@ define void @explicit_pn0_invalid(ptr %p) {
; CHECK-NEXT: [[PTRUE_C_B:%[0-9]+]]:pnr_p8to15 = PTRUE_C_B implicit $vg
; CHECK-NEXT: $pn0 = COPY [[PTRUE_C_B]]
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY [[COPY]]
- ; CHECK-NEXT: INLINEASM &"ld1w { z0.s, z4.s, z8.s, z12.s }, $1/z, [$0]", 1 /* sideeffect attdialect */, 3538954 /* regdef:GPR64common */, def %1, 9 /* reguse */, $pn0, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &"ld1w { z0.s, z4.s, z8.s, z12.s }, $1/z, [$0]", 1 /* sideeffect attdialect */, {{[0-9]+}} /* regdef:GPR64common */, def %1, 9 /* reguse */, $pn0, 2147483657 /* reguse tiedto:$0 */, [[COPY1]](tied-def 3)
; CHECK-NEXT: RET_ReallyLR
%1 = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c8()
%2 = tail call i64 asm sideeffect "ld1w { z0.s, z4.s, z8.s, z12.s }, $1/z, [$0]", "=r,{pn0},0"(target("aarch64.svcount") %1, ptr %p)
diff --git a/llvm/test/CodeGen/AArch64/blr-bti-preserves-operands.mir b/llvm/test/CodeGen/AArch64/blr-bti-preserves-operands.mir
index 760ae4794e3043..6d4f21fdee9507 100644
--- a/llvm/test/CodeGen/AArch64/blr-bti-preserves-operands.mir
+++ b/llvm/test/CodeGen/AArch64/blr-bti-preserves-operands.mir
@@ -8,7 +8,7 @@
# The arguments to the call must become implicit arguments, because the branch
# only expects to get 1 explicit operand which is the branch target.
-# CHECK: BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $sp, implicit-def $wsp, implicit $sp, implicit $x0, implicit $w1 {
+# CHECK: BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $w30_hi, implicit-def $sp, implicit-def $wsp, implicit-def $wsp_hi, implicit $sp, implicit $x0, implicit $w1 {
# CHECK: BL @_setjmp, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1, implicit-def dead $lr, implicit $sp, implicit-def $sp
# CHECK: HINT 36
# CHECK: }
diff --git a/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir b/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
index ffa7453e48b4f0..f9878adfe5e448 100644
--- a/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
+++ b/llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir
@@ -91,10 +91,10 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[LOADgot:%[0-9]+]]:gpr64common = LOADgot target-flags(aarch64-got) @c
; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[LOADgot]], 0 :: (dereferenceable load (s64) from @c)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 3342346 /* regdef:FPR64 */, def %2, 2147483657 /* reguse tiedto:$0 */, [[LDRDui]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 3735562 /* regdef:FPR64 */, def %2, 2147483657 /* reguse tiedto:$0 */, [[LDRDui]](tied-def 3)
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY %2
; CHECK-NEXT: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[LOADgot]], 0 :: (dereferenceable load (s64) from @c)
- ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 3342346 /* regdef:FPR64 */, def %4, 2147483657 /* reguse tiedto:$0 */, [[LDRDui1]](tied-def 3)
+ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 3735562 /* regdef:FPR64 */, def %4, 2147483657 /* reguse tiedto:$0 */, [[LDRDui1]](tied-def 3)
; CHECK-NEXT: [[FNEGDr:%[0-9]+]]:fpr64 = FNEGDr %2
; CHECK-NEXT: nofpexcept FCMPDrr %4, killed [[FNEGDr]], implicit-def $nzcv, implicit $fpcr
; CHECK-NEXT: Bcc 1, %bb.2, implicit $nzcv
@@ -111,10 +111,10 @@ body: |
%6:gpr64common = LOADgot target-flags(aarch64-got) @c
%3:fpr64 = LDRDui %6, 0 :: (dereferenceable load (s64) from @c)
- INLINEASM &"", 1 /* sideeffect attdialect */, 3342346 /* regdef:FPR64 */, def %2, 2147483657 /* reguse tiedto:$0 */, %3(tied-def 3)
+ INLINEASM &"", 1 /* sideeffect attdialect */, 3735562 /* regdef:FPR64 */, def %2, 2147483657 /* reguse tiedto:$0 */, %3(tied-def 3)
%0:fpr64 = COPY %2
%5:fpr64 = LDRDui %6, 0 :: (dereferenceable load (s64) from @c)
- INLINEASM &"", 1 /* sideeffect attdialect */, 3342346 /* regdef:FPR64 */, def %4, 2147483657 /* reguse tiedto:$0 */, %5(tied-def 3)
+ INLINEASM &"", 1 /* sideeffect attdialect */, 3735562 /* regdef:FPR64 */, def %4, 2147483657 /* reguse tiedto:$0 */, %5(tied-def 3)
%7:fpr64 = FNEGDr %2
nofpexcept FCMPDrr %4, killed %7, implicit-def $nzcv, implicit $fpcr
Bcc 1, %bb.2, implicit $nzcv
diff --git a/llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir b/llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
index b1e48346c27464..89102a8c3770d7 100644
--- a/llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
+++ b/llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
@@ -39,7 +39,7 @@
# CHECK: bb.0:
# CHECK-NEXT: liveins:
# CHECK-NEXT: {{ $}}
-# CHECK-NEXT: BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $sp, implicit-def $wsp, implicit-def dead $x0, implicit-def $fp, implicit-def $w29, implicit $x0, implicit $sp, implicit $xzr, implicit $fp {
+# CHECK-NEXT: BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $w30_hi, implicit-def $sp, implicit-def $wsp, implicit-def $wsp_hi, implicit-def dead $x0, implicit-def $fp, implicit-def $w29, implicit-def $w29_hi, implicit $x0, implicit $sp, implicit $xzr, implicit $fp {
# CHECK-NEXT: BLR $x0, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $x0
# CHECK-NEXT: ORRXrs $xzr, $fp, 0
# CHECK-NEXT: BL @attachedcall, implicit-def $lr, implicit internal $sp
@@ -62,7 +62,7 @@ body: |
# CHECK: bb.0:
# CHECK-NEXT: liveins:
# CHECK-NEXT: {{ $}}
-# CHECK-NEXT: BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $sp, implicit-def $wsp, implicit-def dead $x0, implicit-def $fp, implicit-def $w29, implicit $sp, implicit $x0, implicit $xzr, implicit $fp {
+# CHECK-NEXT: BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $w30_hi, implicit-def $sp, implicit-def $wsp, implicit-def $wsp_hi, implicit-def dead $x0, implicit-def $fp, implicit-def $w29, implicit-def $w29_hi, implicit $sp, implicit $x0, implicit $xzr, implicit $fp {
# CHECK-NEXT: BL @foo, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $x0
# CHECK-NEXT: $fp = ORRXrs $xzr, $fp, 0
# CHECK-NEXT: BL @attachedcall, implicit-def $lr, implicit internal $sp
@@ -82,7 +82,7 @@ body: |
# CHECK: bb.0:
# CHECK-NEXT: liveins:
# CHECK-NEXT: {{ $}}
-# CHECK-NEXT: BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $sp, implicit-def $wsp, implicit-def $x0, implicit-def $w0, implicit-def $fp, implicit-def $w29, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $xzr, implicit $fp {
+# CHECK-NEXT: BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $w30_hi, implicit-def $sp, implicit-def $wsp, implicit-def $wsp_hi, implicit-def $x0, implicit-def $w0, implicit-def $w0_hi, implicit-def $fp, implicit-def $w29, implicit-def $w29_hi, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $xzr, implicit $fp {
# CHECK-NEXT: BL @foo, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $x0
# CHECK-NEXT: $fp = ORRXrs $xzr, $fp, 0
# CHECK-NEXT: BL @attachedcall, implicit-def $lr, implicit internal $sp
@@ -102,7 +102,7 @@ body: |
# CHECK: bb.0:
# CHECK-NEXT: liveins:
# CHECK-NEXT: {{ $}}
-# CHECK-NEXT: BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $sp, implicit-def $wsp, implicit-def dead $x0, implicit-def $fp, implicit-def $w29, implicit $sp, implicit $w0, implicit $w1, implicit $xzr, implicit $fp {
+# CHECK-NEXT: BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $w30_hi, implicit-def $sp, implicit-def $wsp, implicit-def $wsp_hi, implicit-def dead $x0, implicit-def $fp, implicit-def $w29, implicit-def $w29_hi, implicit $sp, implicit $w0, implicit $w1, implicit $xzr, implicit $fp {
# CHECK-NEXT: BL @foo, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit $w1, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $x0
# CHECK-NEXT: $fp = ORRXrs $xzr, $fp, 0
# CHECK-NEXT: BL @attachedcall, implicit-def $lr, implicit internal $sp
@@ -123,7 +123,7 @@ body: |
# CHECK: bb.0:
# CHECK-NEXT: liveins:
# CHECK-NEXT: {{ $}}
-# CHECK-NEXT: BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $sp, implicit-def $wsp, implicit-def dead $x0, implicit-def $fp, implicit-def $w29, implicit $x8, implicit $sp, implicit $w0, implicit $w1, implicit $xzr, implicit $fp {
+# CHECK-NEXT: BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $w30_hi, implicit-def $sp, implicit-def $wsp, implicit-def $wsp_hi, implicit-def dead $x0, implicit-def $fp, implicit-def $w29, implicit-def $w29_hi, implicit $x8, implicit $sp, implicit $w0, implicit $w1, implicit $xzr, implicit $fp {
# CHECK-NEXT: BLR $x8, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit $w1, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $x0
# CHECK-NEXT: $fp = ORRXrs $xzr, $fp, 0
# CHECK-NEXT: BL @attachedcall, implicit-def $lr, implicit internal $sp
@@ -145,7 +145,7 @@ body: |
# CHECK: bb.0:
# CHECK-NEXT: liveins:
# CHECK-NEXT: {{ $}}
-# CHECK-NEXT: BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $sp, implicit-def $wsp, implicit-def dead $x0, implicit-def $fp, implicit-def $w29, implicit $sp, implicit undef $x0, implicit $xzr, implicit $fp {
+# CHECK-NEXT: BUNDLE implicit-def $lr, implicit-def $w30, implicit-def $w30_hi, implicit-def $sp, implicit-def $wsp, implicit-def $wsp_hi, implicit-def dead $x0, implicit-def $fp, implicit-def $w29, implicit-def $w29_hi, implicit $sp, implicit undef $x0, implicit $xzr, implicit $fp {
# CHECK-NEXT: BL @foo, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit undef $x0, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def dead $x0
# CHECK-NEXT: $fp = ORRXrs $xzr, $fp, 0
# CHECK-NEXT: BL @objc_retainAutoreleasedReturnValue, implicit-def $lr, implicit internal $sp
diff --git a/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir b/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
index 8e29255189bf53..a10d7588cb4429 100644
--- a/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
+++ b/llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
@@ -155,7 +155,7 @@ body: |
; CHECK: liveins: $q0, $q1, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $q1 = LDRQui renamable $x1, 1 :: (load (s128))
- ; CHECK-NEXT: early-clobber renamable $x1, renamable $q0 = LDRQpre renamable $x1, 48, implicit $w1 :: (load (s128))
+ ; CHECK-NEXT: early-clobber renamable $x1, renamable $q0 = LDRQpre renamable $x1, 48, implicit $w1, implicit $w1_hi :: (load (s128))
; CHECK-NEXT: STPQi renamable $q0, renamable $q1, renamable $x1, 0 :: (store (s128))
; CHECK-NEXT: RET undef $lr
renamable $q1 = LDRQui renamable $x1, 1 :: (load (s128))
@@ -246,7 +246,7 @@ body: |
; CHECK-LABEL: name: 9-ldrspre-ldrsui-mod-base-reg-no-merge
; CHECK: liveins: $s0, $s1, $x0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: dead early-clobber renamable $x1, renamable $s0 = LDRSpre renamable $x1, 12, implicit $w1 :: (load (s32))
+ ; CHECK-NEXT: dead early-clobber renamable $x1, renamable $s0 = LDRSpre renamable $x1, 12, implicit $w1, implicit $w1_hi :: (load (s32))
; CHECK-NEXT: renamable $x1 = LDRXui renamable $x0, 1 :: (load (s64))
; CHECK-NEXT: renamable $s1 = LDRSui renamable $x1, 1 :: (load (s32))
; CHECK-NEXT: STPSi renamable $s0, renamable $s1, renamable $x1, 0 :: (store (s32))
@@ -280,7 +280,7 @@ body: |
; CHECK-LABEL: name: 10-ldrspre-ldrsui-used-base-reg-no-merge
; CHECK: liveins: $s0, $s1, $x0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $x1, renamable $s0 = LDRSpre renamable $x1, 12, implicit $w1 :: (load (s32))
+ ; CHECK-NEXT: early-clobber renamable $x1, renamable $s0 = LDRSpre renamable $x1, 12, implicit $w1, implicit $w1_hi :: (load (s32))
; CHECK-NEXT: renamable $x0 = LDRXui renamable $x1, 1 :: (load (s64))
; CHECK-NEXT: STRXui renamable $x0, renamable $x0, 1 :: (store (s64))
; CHECK-NEXT: renamable $s1 = LDRSui renamable $x1, 1 :: (load (s32))
@@ -315,12 +315,12 @@ body: |
; CHECK-LABEL: name: 11-ldrqpre-ldrqpre-no-merge
; CHECK: liveins: $q0, $q1, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $x1, dead renamable $q0 = LDRQpre renamable $x1, 48, implicit $w1 :: (load (s128))
- ; CHECK-NEXT: early-clobber renamable $x1, dead renamable $q1 = LDRQpre renamable $x1, 1, implicit $w1 :: (load (s128))
- ; CHECK-NEXT: early-clobber renamable $x1, dead renamable $q0 = LDRQpre renamable $x1, 16, implicit $w1 :: (load (s128))
- ; CHECK-NEXT: early-clobber renamable $x1, dead renamable $q1 = LDRQpre renamable $x1, 12, implicit $w1 :: (load (s128))
- ; CHECK-NEXT: early-clobber renamable $x1, renamable $q0 = LDRQpre renamable $x1, 16, implicit $w1 :: (load (s128))
- ; CHECK-NEXT: early-clobber renamable $x1, renamable $q1 = LDRQpre renamable $x1, 16, implicit $w1 :: (load (s128))
+ ; CHECK-NEXT: early-clobber renamable $x1, dead renamable $q0 = LDRQpre renamable $x1, 48, implicit $w1, implicit $w1_hi :: (load (s128))
+ ; CHECK-NEXT: early-clobber renamable $x1, dead renamable $q1 = LDRQpre renamable $x1, 1, implicit $w1, implicit $w1_hi :: (load (s128))
+ ; CHECK-NEXT: early-clobber renamable $x1, dead renamable $q0 = LDRQpre renamable $x1, 16, implicit $w1, implicit $w1_hi :: (load (s128))
+ ; CHECK-NEXT: early-clobber renamable $x1, dead renamable $q1 = LDRQpre renamable $x1, 12, implicit $w1, implicit $w1_hi :: (load (s128))
+ ; CHECK-NEXT: early-clobber renamable $x1, renamable $q0 = LDRQpre renamable $x1, 16, implicit $w1, implicit $w1_hi :: (load (s128))
+ ; CHECK-NEXT: early-clobber renamable $x1, renamable $q1 = LDRQpre renamable $x1, 16, implicit $w1, implicit $w1_hi :: (load (s128))
; CHECK-NEXT: STPQi renamable $q0, renamable $q1, renamable $x1, 0 :: (store (s128))
; CHECK-NEXT: RET undef $lr
early-clobber renamable $x1, renamable $q0 = LDRQpre killed renamable $x1, 48 :: (load (s128))
@@ -352,7 +352,7 @@ body: |
; CHECK-LABEL: name: 12-ldrspre-ldrsui-no-merge
; CHECK: liveins: $s0, $s1, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $x1, renamable $s0 = LDRSpre renamable $x1, 12, implicit $w1 :: (load (s32))
+ ; CHECK-NEXT: early-clobber renamable $x1, renamable $s0 = LDRSpre renamable $x1, 12, implicit $w1, implicit $w1_hi :: (load (s32))
; CHECK-NEXT: renamable $s1 = LDRSui renamable $x1, 2 :: (load (s32))
; CHECK-NEXT: STPSi renamable $s0, renamable $s1, renamable $x1, 0 :: (store (s32))
; CHECK-NEXT: RET undef $lr
@@ -383,7 +383,7 @@ body: |
; CHECK-LABEL: name: 13-ldrqpre-ldrdui-no-merge
; CHECK: liveins: $d1, $q0, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $x1, renamable $q0 = LDRQpre renamable $x1, 32, implicit $w1 :: (load (s128))
+ ; CHECK-NEXT: early-clobber renamable $x1, renamable $q0 = LDRQpre renamable $x1, 32, implicit $w1, implicit $w1_hi :: (load (s128))
; CHECK-NEXT: renamable $d1 = LDRDui renamable $x1, 1 :: (load (s64))
; CHECK-NEXT: STRQui renamable $q0, renamable $x1, 0 :: (store (s128))
; CHECK-NEXT: STRDui renamable $d1, renamable $x1, 1 :: (store (s64))
@@ -415,7 +415,7 @@ body: |
; CHECK-LABEL: name: 14-ldrqpre-strqui-no-merge
; CHECK: liveins: $q0, $q1, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $x1, renamable $q0 = LDRQpre renamable $x1, 32, implicit $w1 :: (load (s128))
+ ; CHECK-NEXT: early-clobber renamable $x1, renamable $q0 = LDRQpre renamable $x1, 32, implicit $w1, implicit $w1_hi :: (load (s128))
; CHECK-NEXT: STRQui renamable $q0, renamable $x1, 0 :: (store (s128))
; CHECK-NEXT: RET undef $lr
early-clobber renamable $x1, renamable $q0 = LDRQpre killed renamable $x1, 32 :: (load (s128))
@@ -473,7 +473,7 @@ body: |
; CHECK-LABEL: name: 16-ldrqpre-ldrqui-diff-base-reg-no-merge
; CHECK: liveins: $q0, $q1, $x1, $x2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $x1, renamable $q0 = LDRQpre renamable $x1, 32, implicit $w1 :: (load (s128))
+ ; CHECK-NEXT: early-clobber renamable $x1, renamable $q0 = LDRQpre renamable $x1, 32, implicit $w1, implicit $w1_hi :: (load (s128))
; CHECK-NEXT: renamable $q1 = LDRQui renamable $x2, 1 :: (load (s128))
; CHECK-NEXT: STPQi renamable $q0, renamable $q1, renamable $x1, 0 :: (store (s128))
; CHECK-NEXT: RET undef $lr
@@ -534,7 +534,7 @@ body: |
; CHECK-LABEL: name: 18-ldrqpre-ldurqi-no-merge
; CHECK: liveins: $q0, $q1, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $x1, renamable $q0 = LDRQpre renamable $x1, 32, implicit $w1 :: (load (s128))
+ ; CHECK-NEXT: early-clobber renamable $x1, renamable $q0 = LDRQpre renamable $x1, 32, implicit $w1, implicit $w1_hi :: (load (s128))
; CHECK-NEXT: renamable $q1 = LDURQi renamable $x1, 1 :: (load (s128))
; CHECK-NEXT: STPQi renamable $q0, renamable $q1, renamable $x1, 0 :: (store (s128))
; CHECK-NEXT: RET undef $lr
@@ -587,7 +587,7 @@ body: |
; CHECK-LABEL: name: 20-ldrspre-ldrsui-unaligned-no-merge
; CHECK: liveins: $s0, $s1, $x1
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $x1, renamable $s0 = LDRSpre renamable $x1, 251, implicit $w1 :: (load (s32))
+ ; CHECK-NEXT: early-clobber renamable $x1, renamable $s0 = LDRSpre renamable $x1, 251, implicit $w1, implicit $w1_hi :: (load (s32))
; CHECK-NEXT: renamable $s1 = LDRSui renamable $x1, 1 :: (load (s32))
; CHECK-NEXT: STPSi renamable $s0, renamable $s1, renamable $x1, 0 :: (store (s32))
; CHECK-NEXT: RET undef $lr
@@ -667,7 +667,7 @@ body: |
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $x2 = LDRSWui renamable $x1, 1 :: (load (s32))
- ; CHECK-NEXT: early-clobber renamable $x1, renamable $x0 = LDRSWpre renamable $x1, 40, implicit $w1 :: (load (s32))
+ ; CHECK-NEXT: early-clobber renamable $x1, renamable $x0 = LDRSWpre renamable $x1, 40, implicit $w1, implicit $w1_hi :: (load (s32))
; CHECK-NEXT: STPXi renamable $x0, renamable $x2, renamable $x1, 0 :: (store (s64))
; CHECK-NEXT: RET undef $lr
renamable $x2 = LDRSWui renamable $x1, 1 :: (load (s32))
@@ -694,7 +694,7 @@ body: |
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $x2 = LDURSWi renamable $x1, 4 :: (load (s32))
- ; CHECK-NEXT: early-clobber renamable $x1, renamable $x0 = LDRSWpre renamable $x1, 40, implicit $w1 :: (load (s32))
+ ; CHECK-NEXT: early-clobber renamable $x1, renamable $x0 = LDRSWpre renamable $x1, 40, implicit $w1, implicit $w1_hi :: (load (s32))
; CHECK-NEXT: STPXi renamable $x0, renamable $x2, renamable $x1, 0 :: (store (s64))
; CHECK-NEXT: RET undef $lr
renamable $x2 = LDURSWi renamable $x1, 4 :: (load (s32))
@@ -720,12 +720,12 @@ body: |
; CHECK-LABEL: name: 25-ldrswpre-ldrswpre-no-merge
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $x1, dead renamable $x0 = LDRSWpre renamable $x1, 48, implicit $w1 :: (load (s32))
- ; CHECK-NEXT: early-clobber renamable $x1, dead renamable $x2 = LDRSWpre renamable $x1, 1, implicit $w1 :: (load (s32))
- ; CHECK-NEXT: early-clobber renamable $x1, dead renamable $x0 = LDRSWpre renamable $x1, 16, implicit $w1 :: (load (s32))
- ; CHECK-NEXT: early-clobber renamable $x1, dead renamable $x2 = LDRSWpre renamable $x1, 12, implicit $w1 :: (load (s32))
- ; CHECK-NEXT: early-clobber renamable $x1, renamable $x0 = LDRSWpre renamable $x1, 16, implicit $w1 :: (load (s32))
- ; CHECK-NEXT: early-clobber renamable $x1, renamable $x2 = LDRSWpre renamable $x1, 16, implicit $w1 :: (load (s32))
+ ; CHECK-NEXT: early-clobber renamable $x1, dead renamable $x0 = LDRSWpre renamable $x1, 48, implicit $w1, implicit $w1_hi :: (load (s32))
+ ; CHECK-NEXT: early-clobber renamable $x1, dead renamable $x2 = LDRSWpre renamable $x1, 1, implicit $w1, implicit $w1_hi :: (load (s32))
+ ; CHECK-NEXT: early-clobber renamable $x1, dead renamable $x0 = LDRSWpre renamable $x1, 16, implicit $w1, implicit $w1_hi :: (load (s32))
+ ; CHECK-NEXT: early-clobber renamable $x1, dead renamable $x2 = LDRSWpre renamable $x1, 12, implicit $w1, implicit $w1_hi :: (load (s32))
+ ; CHECK-NEXT: early-clobber renamable $x1, renamable $x0 = LDRSWpre renamable $x1, 16, implicit $w1, implicit $w1_hi :: (load (s32))
+ ; CHECK-NEXT: early-clobber renamable $x1, renamable $x2 = LDRSWpre renamable $x1, 16, implicit $w1, implicit $w1_hi :: (load (s32))
; CHECK-NEXT: STPXi renamable $x0, renamable $x2, renamable $x1, 0 :: (store (s64))
; CHECK-NEXT: RET undef $lr
early-clobber renamable $x1, renamable $x0 = LDRSWpre killed renamable $x1, 48 :: (load (s32))
@@ -755,8 +755,8 @@ body: |
; CHECK-LABEL: name: 26-ldrswpre-ldrwui-no-merge
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $x1, renamable $x0 = LDRSWpre renamable $x1, 40, implicit $w1 :: (load (s32))
- ; CHECK-NEXT: renamable $w2 = LDRWui renamable $x1, 1, implicit-def $x2 :: (load (s32))
+ ; CHECK-NEXT: early-clobber renamable $x1, renamable $x0 = LDRSWpre renamable $x1, 40, implicit $w1, implicit $w1_hi :: (load (s32))
+ ; CHECK-NEXT: renamable $w2 = LDRWui renamable $x1, 1, implicit-def $x2, implicit $w2_hi :: (load (s32))
; CHECK-NEXT: STPXi renamable $x0, renamable $x2, renamable $x1, 0 :: (store (s64))
; CHECK-NEXT: RET undef $lr
early-clobber renamable $x1, renamable $x0 = LDRSWpre killed renamable $x1, 40 :: (load (s32))
@@ -782,7 +782,7 @@ body: |
; CHECK-LABEL: name: 27-ldrwpre-ldrswui-no-merge
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $x1, renamable $w0 = LDRWpre renamable $x1, 40, implicit $w1 :: (load (s32))
+ ; CHECK-NEXT: early-clobber renamable $x1, renamable $w0 = LDRWpre renamable $x1, 40, implicit $w1, implicit $w1_hi :: (load (s32))
; CHECK-NEXT: renamable $x2 = LDRSWui renamable $x1, 1 :: (load (s32))
; CHECK-NEXT: STPXi renamable $x0, renamable $x2, renamable $x1, 0 :: (store (s64))
; CHECK-NEXT: RET undef $lr
@@ -808,9 +808,9 @@ body: |
; CHECK-LABEL: name: 28-ldrswpre-ldrwpre-no-merge
; CHECK: liveins: $x11, $x13
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $x11, dead renamable $x10 = LDRSWpre renamable $x11, 8, implicit $w11 :: (load (s32), align 8)
+ ; CHECK-NEXT: early-clobber renamable $x11, dead renamable $x10 = LDRSWpre renamable $x11, 8, implicit $w11, implicit $w11_hi :: (load (s32), align 8)
; CHECK-NEXT: $x14 = EORXrs renamable $x11, renamable $x13, 0
- ; CHECK-NEXT: early-clobber renamable $x11, dead renamable $w12 = LDRWpre renamable $x11, 4, implicit $w11 :: (load (s32))
+ ; CHECK-NEXT: early-clobber renamable $x11, dead renamable $w12 = LDRWpre renamable $x11, 4, implicit $w11, implicit $w11_hi :: (load (s32))
; CHECK-NEXT: $x13 = EORXrs renamable $x11, renamable $x13, 0
; CHECK-NEXT: STPXi renamable $x13, renamable $x14, renamable $x11, 0 :: (store (s64))
; CHECK-NEXT: RET undef $lr
@@ -838,9 +838,9 @@ body: |
; CHECK-LABEL: name: 29-ldrwpre-ldrswpre-no-merge
; CHECK: liveins: $x11, $x13
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: early-clobber renamable $x11, dead renamable $w12 = LDRWpre renamable $x11, 8, implicit $w11 :: (load (s32))
+ ; CHECK-NEXT: early-clobber renamable $x11, dead renamable $w12 = LDRWpre renamable $x11, 8, implicit $w11, implicit $w11_hi :: (load (s32))
; CHECK-NEXT: $x14 = EORXrs renamable $x11, renamable $x13, 0
- ; CHECK-NEXT: early-clobber renamable $x11, dead renamable $x10 = LDRSWpre renamable $x11, 4, implicit $w11 :: (load (s32), align 8)
+ ; CHECK-NEXT: early-clobber renamable $x11, dead renamable $x10 = LDRSWpre renamable $x11, 4, implicit $w11, implicit $w11_hi :: (load (s32), align 8)
; CHECK-NEXT: $x13 = EORXrs renamable $x11, renamable $x13, 0
; CHECK-NEXT: STPXi renamable $x13, renamable $x14, renamable $x11, 0 :: (store (s64))
; CHECK-NEXT: RET undef $lr
diff --git a/llvm/test/CodeGen/AArch64/machine-outliner-calls.mir b/llvm/test/CodeGen/AArch64/machine-outliner-calls.mir
index 8abd56fa205499..700a5b228122fc 100644
--- a/llvm/test/CodeGen/AArch64/machine-outliner-calls.mir
+++ b/llvm/test/CodeGen/AArch64/machine-outliner-calls.mir
@@ -57,7 +57,7 @@ body: |
# CHECK: name: OUTLINED_FUNCTION_0
# CHECK: bb.0:
-# CHECK: liveins: $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $d15, $d8, $d9, $d10, $d11, $d12, $d13, $d14, $lr
+# CHECK: liveins: $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27, $x28, $d8, $d9, $d10, $d11, $d12, $d13, $d14, $d15, $lr
# CHECK-DAG: frame-setup CFI_INSTRUCTION def_cfa_offset 16
# CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w30, -16
# CHECK-NEXT: early-clobber $sp = STRXpre $lr, $sp, -16
diff --git a/llvm/test/CodeGen/AArch64/misched-bundle.mir b/llvm/test/CodeGen/AArch64/misched-bundle.mir
index 9adcd2904a250a..ac6112e8c60efa 100644
--- a/llvm/test/CodeGen/AArch64/misched-bundle.mir
+++ b/llvm/test/CodeGen/AArch64/misched-bundle.mir
@@ -17,13 +17,18 @@
# CHECK-NEXT: Single Issue : false;
# CHECK-NEXT: SU(1): renamable $z1 = LD1H renamable $p0, renamable $x2, renamable $x10 :: (load unknown-size, align 1)
# CHECK-NEXT: # preds left : 0
-# CHECK-NEXT: # succs left : 4
+# CHECK-NEXT: # succs left : 9
# CHECK-NEXT: # rdefs left : 0
# CHECK-NEXT: Latency : 3
# CHECK-NEXT: Depth : 0
# CHECK-NEXT: Height : 7
# CHECK-NEXT: Successors:
# CHECK-NEXT: SU(7): Out Latency=1
+# CHECK-NEXT: SU(7): Out Latency=1
+# CHECK-NEXT: SU(7): Out Latency=1
+# CHECK-NEXT: SU(7): Out Latency=1
+# CHECK-NEXT: SU(7): Out Latency=1
+# CHECK-NEXT: SU(7): Out Latency=1
# CHECK-NEXT: SU(6): Data Latency=3 Reg=$z1
# CHECK-NEXT: SU(9): Ord Latency=0 Memory
# CHECK-NEXT: SU(8): Ord Latency=0 Memory
@@ -78,7 +83,7 @@
# CHECK-NEXT: Single Issue : false;
# CHECK-NEXT: SU(6): $z0 = FMAD_ZPmZZ_H renamable $p0, killed $z0(tied-def 0), killed renamable $z1, killed renamable $z2
# CHECK-NEXT: # preds left : 4
-# CHECK-NEXT: # succs left : 2
+# CHECK-NEXT: # succs left : 7
# CHECK-NEXT: # rdefs left : 0
# CHECK-NEXT: Latency : 4
# CHECK-NEXT: Depth : 3
@@ -91,9 +96,14 @@
# CHECK-NEXT: Successors:
# CHECK-NEXT: SU(8): Data Latency=4 Reg=$z0
# CHECK-NEXT: SU(7): Anti Latency=0
+# CHECK-NEXT: SU(7): Anti Latency=0
+# CHECK-NEXT: SU(7): Anti Latency=0
+# CHECK-NEXT: SU(7): Anti Latency=0
+# CHECK-NEXT: SU(7): Anti Latency=0
+# CHECK-NEXT: SU(7): Anti Latency=0
# CHECK-NEXT: Single Issue : false;
# CHECK-NEXT: SU(7): BUNDLE implicit-def $z1, implicit-def $q1, implicit-def $d1, implicit-def $s1, implicit-def $h1, implicit-def $b1, implicit $z5, implicit $p0, implicit killed $z4, implicit killed $z3
-# CHECK-NEXT: # preds left : 5
+# CHECK-NEXT: # preds left : 15
# CHECK-NEXT: # succs left : 1
# CHECK-NEXT: # rdefs left : 0
# CHECK-NEXT: Latency : 1
@@ -101,10 +111,20 @@
# CHECK-NEXT: Height : 4
# CHECK-NEXT: Predecessors:
# CHECK-NEXT: SU(6): Anti Latency=0
+# CHECK-NEXT: SU(6): Anti Latency=0
+# CHECK-NEXT: SU(6): Anti Latency=0
+# CHECK-NEXT: SU(6): Anti Latency=0
+# CHECK-NEXT: SU(6): Anti Latency=0
+# CHECK-NEXT: SU(6): Anti Latency=0
# CHECK-NEXT: SU(5): Data Latency=3 Reg=$z5
# CHECK-NEXT: SU(4): Data Latency=3 Reg=$z4
# CHECK-NEXT: SU(3): Data Latency=3 Reg=$z3
# CHECK-NEXT: SU(1): Out Latency=1
+# CHECK-NEXT: SU(1): Out Latency=1
+# CHECK-NEXT: SU(1): Out Latency=1
+# CHECK-NEXT: SU(1): Out Latency=1
+# CHECK-NEXT: SU(1): Out Latency=1
+# CHECK-NEXT: SU(1): Out Latency=1
# CHECK-NEXT: Successors:
# CHECK-NEXT: SU(9): Data Latency=4 Reg=$z1
# CHECK-NEXT: Single Issue : false;
diff --git a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
index 6cdbbb8c53d690..6fb8ba2dfc839e 100644
--- a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
+++ b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-01.mir
@@ -1583,6 +1583,18 @@ body: |
# CHECK-NEXT: B0 [0B,48r:0)[192r,224r:1) 0 at 0B-phi 1 at 192r
# CHECK-NEXT: B1 [0B,88r:0)[208r,224r:1) 0 at 0B-phi 1 at 208r
# CHECK-NEXT: B2 [0B,96r:0) 0 at 0B-phi
+# CHECK-NEXT: B0_HI [0B,48r:0)[192r,224r:1) 0 at 0B-phi 1 at 192r
+# CHECK-NEXT: H0_HI [0B,48r:0)[192r,224r:1) 0 at 0B-phi 1 at 192r
+# CHECK-NEXT: S0_HI [0B,48r:0)[192r,224r:1) 0 at 0B-phi 1 at 192r
+# CHECK-NEXT: B1_HI [0B,88r:0)[208r,224r:1) 0 at 0B-phi 1 at 208r
+# CHECK-NEXT: H1_HI [0B,88r:0)[208r,224r:1) 0 at 0B-phi 1 at 208r
+# CHECK-NEXT: S1_HI [0B,88r:0)[208r,224r:1) 0 at 0B-phi 1 at 208r
+# CHECK-NEXT: B2_HI [0B,96r:0) 0 at 0B-phi
+# CHECK-NEXT: H2_HI [0B,96r:0) 0 at 0B-phi
+# CHECK-NEXT: S2_HI [0B,96r:0) 0 at 0B-phi
+# CHECK-NEXT: D0_HI [0B,48r:0)[192r,224r:1) 0 at 0B-phi 1 at 192r
+# CHECK-NEXT: D1_HI [0B,88r:0)[208r,224r:1) 0 at 0B-phi 1 at 208r
+# CHECK-NEXT: D2_HI [0B,96r:0) 0 at 0B-phi
# CHECK-NEXT: %0 [48r,168r:0) 0 at 48r weight:0.000000e+00
# CHECK-NEXT: %1 [88r,120r:0) 0 at 88r weight:0.000000e+00
# CHECK-NEXT: %2 [96r,128r:0) 0 at 96r weight:0.000000e+00
diff --git a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
index 2cc63018813817..9c9b6e281b15da 100644
--- a/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
+++ b/llvm/test/CodeGen/AArch64/misched-detail-resource-booking-02.mir
@@ -466,6 +466,9 @@ body: |
# CHECK-NEXT: W0 [0B,16r:0) 0 at 0B-phi
# CHECK-NEXT: W1 [0B,32r:0) 0 at 0B-phi
# CHECK-NEXT: W2 [0B,48r:0) 0 at 0B-phi
+# CHECK-NEXT: W0_HI [0B,16r:0) 0 at 0B-phi
+# CHECK-NEXT: W1_HI [0B,32r:0) 0 at 0B-phi
+# CHECK-NEXT: W2_HI [0B,48r:0) 0 at 0B-phi
# CHECK-NEXT: RegMasks:
# CHECK-NEXT: ********** MACHINEINSTRS **********
# CHECK-NEXT: # Machine code for function f: IsSSA, NoPHIs, TracksLiveness, NoVRegs
@@ -476,4 +479,4 @@ body: |
# CHECK-NEXT: 32B $x4 = ADDXrr $x1, $x1
# CHECK-NEXT: 48B $x5 = ADDXrr $x2, $x2
# CHECK-EMPTY:
-# CHECK-NEXT: # End machine code for function f.
\ No newline at end of file
+# CHECK-NEXT: # End machine code for function f.
diff --git a/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir b/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
index f8af5b96370178..3174d3c8c1a737 100644
--- a/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
+++ b/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
@@ -487,7 +487,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[DEF]]
- ; CHECK-NEXT: INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 3342346 /* regdef:FPR64 */, def %1, 262158 /* mem:m */, killed [[COPY1]]
+ ; CHECK-NEXT: INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 3735562 /* regdef:FPR64 */, def %1, 262158 /* mem:m */, killed [[COPY1]]
; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub
; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
@@ -505,7 +505,7 @@ body: |
%0:gpr64common = COPY $x0
%2:gpr64all = IMPLICIT_DEF
%3:gpr64sp = COPY %2
- INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 3342346 /* regdef:FPR64 */, def %1, 262158 /* mem:m */, killed %3
+ INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 3735562 /* regdef:FPR64 */, def %1, 262158 /* mem:m */, killed %3
%4:fpr128 = MOVIv2d_ns 0
%5:fpr64 = COPY %4.dsub
%7:fpr128 = IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AArch64/preserve.ll b/llvm/test/CodeGen/AArch64/preserve.ll
index 5839bb5440a9b0..bafcc748ed36d8 100644
--- a/llvm/test/CodeGen/AArch64/preserve.ll
+++ b/llvm/test/CodeGen/AArch64/preserve.ll
@@ -4,20 +4,19 @@
target triple = "aarch64-unknown-unknown"
declare void @bar1()
define preserve_mostcc void @baz() #0 {
-; CHECK: baz Clobbered Registers: $ffr $fpcr $fpmr $fpsr $nzcv $sp $vg $wsp $za $b0 $b1 $b2 $b3 $b4 $b5 $b6 $b7 $b16 $b17 $b18 $b19 $b20 $b21 $b22 $b23 $b24 $b25 $b26 $b27 $b28 $b29 $b30 $b31 $d0 $d1 $d2 $d3 $d4 $d5 $d6 $d7 $d16 $d17 $d18 $d19 $d20 $d21 $d22 $d23 $d24 $d25 $d26 $d27 $d28 $d29 $d30 $d31 $h0 $h1 $h2 $h3 $h4 $h5 $h6 $h7 $h16 $h17 $h18 $h19 $h20 $h21 $h22 $h23 $h24 $h25 $h26 $h27 $h28 $h29 $h30 $h31 $p0 $p1 $p2 $p3 $p4 $p5 $p6 $p7 $p8 $p9 $p10 $p11 $p12 $p13 $p14 $p15 $pn0 $pn1 $pn2 $pn3 $pn4 $pn5 $pn6 $pn7 $pn8 $pn9 $pn10 $pn11 $pn12 $pn13 $pn14 $pn15 $q0 $q1 $q2 $q3 $q4 $q5 $q6 $q7 $q8 $q9 $q10 $q11 $q12 $q13 $q14 $q15 $q16 $q17 $q18 $q19 $q20 $q21 $q22 $q23 $q24 $q25 $q26 $q27 $q28 $q29 $q30 $q31 $s0 $s1 $s2 $s3 $s4 $s5 $s6 $s7 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 $s28 $s29 $s30 $s31 $w0 $w1 $w2 $w3 $w4 $w5 $w6 $w7 $w8 $w16 $w17 $w18 $x0 $x1 $x2 $x3 $x4 $x5 $x6 $x7 $x8 $x16 $x17 $x18 $z0 $z1 $z2 $z3 $z4 $z5 $z6 $z7 $z8 $z9 $z10 $z11 $z12 $z13 $z14 $z15 $z16 $z17 $z18 $z19 $z20 $z21 $z22 $z23 $z24 $z25 $z26 $z27 $z28 $z29 $z30 $z31 $zab0 $zad0 $zad1 $zad2 $zad3 $zad4 $zad5 $zad6 $zad7 $zah0 $zah1 $zaq0 $zaq1 $zaq2 $zaq3 $zaq4 $zaq5 $zaq6 $zaq7 $zaq8 $zaq9 $zaq10 $zaq11 $zaq12 $zaq13 $zaq14 $zaq15 $zas0 $zas1 $zas2 $zas3 $zt0 $d0_d1 $d1_d2 $d2_d3 $d3_d4 $d4_d5 $d5_d6 $d6_d7 $d7_d8 $d15_d16 $d16_d17 $d17_d18 $d18_d19 $d19_d20 $d20_d21 $d21_d22 $d22_d23 $d23_d24 $d24_d25 $d25_d26 $d26_d27 $d27_d28 $d28_d29 $d29_d30 $d30_d31 $d31_d0 $d0_d1_d2_d3 $d1_d2_d3_d4 $d2_d3_d4_d5 $d3_d4_d5_d6 $d4_d5_d6_d7 $d5_d6_d7_d8 $d6_d7_d8_d9 $d7_d8_d9_d10 $d13_d14_d15_d16 $d14_d15_d16_d17 $d15_d16_d17_d18 $d16_d17_d18_d19 $d17_d18_d19_d20 $d18_d19_d20_d21 $d19_d20_d21_d22 $d20_d21_d22_d23 $d21_d22_d23_d24 $d22_d23_d24_d25 $d23_d24_d25_d26 $d24_d25_d26_d27 $d25_d26_d27_d28 $d26_d27_d28_d29 $d27_d28_d29_d30 $d28_d29_d30_d31 $d29_d30_d31_d0 $d30_d31_d0_d1 $d31_d0_d1_d2 $d0_d1_d2 $d1_d2_d3 $d2_d3_d4 $d3_d4_d5 $d4_d5_d6 $d5_d6_d7 $d6_d7_d8 $d7_d8_d9 $d14_d15_d16 $d15_d16_d17 $d16_d17_d18 $d17_d18_d19 $d18_d19_d20 $d19_d20_d21 $d20_d21_d22 $d21_d22_d23 $d22_d23_d24 $d23_d24_d25 $d24_d25_d26 $d25_d26_d27 $d26_d27_d28 $d27_d28_d29 $d28_d29_d30 $d29_d30_d31 $d30_d31_d0 $d31_d0_d1 $p0_p1 $p1_p2 $p2_p3 $p3_p4 $p4_p5 $p5_p6 $p6_p7 $p7_p8 $p8_p9 $p9_p10 $p10_p11 $p11_p12 $p12_p13 $p13_p14 $p14_p15 $p15_p0 $q0_q1 $q1_q2 $q2_q3 $q3_q4 $q4_q5 $q5_q6 $q6_q7 $q7_q8 $q8_q9 $q9_q10 $q10_q11 $q11_q12 $q12_q13 $q13_q14 $q14_q15 $q15_q16 $q16_q17 $q17_q18 $q18_q19 $q19_q20 $q20_q21 $q21_q22 $q22_q23 $q23_q24 $q24_q25 $q25_q26 $q26_q27 $q27_q28 $q28_q29 $q29_q30 $q30_q31 $q31_q0 $q0_q1_q2_q3 $q1_q2_q3_q4 $q2_q3_q4_q5 $q3_q4_q5_q6 $q4_q5_q6_q7 $q5_q6_q7_q8 $q6_q7_q8_q9 $q7_q8_q9_q10 $q8_q9_q10_q11 $q9_q10_q11_q12 $q10_q11_q12_q13 $q11_q12_q13_q14 $q12_q13_q14_q15 $q13_q14_q15_q16 $q14_q15_q16_q17 $q15_q16_q17_q18 $q16_q17_q18_q19 $q17_q18_q19_q20 $q18_q19_q20_q21 $q19_q20_q21_q22 $q20_q21_q22_q23 $q21_q22_q23_q24 $q22_q23_q24_q25 $q23_q24_q25_q26 $q24_q25_q26_q27 $q25_q26_q27_q28 $q26_q27_q28_q29 $q27_q28_q29_q30 $q28_q29_q30_q31 $q29_q30_q31_q0 $q30_q31_q0_q1 $q31_q0_q1_q2 $q0_q1_q2 $q1_q2_q3 $q2_q3_q4 $q3_q4_q5 $q4_q5_q6 $q5_q6_q7 $q6_q7_q8 $q7_q8_q9 $q8_q9_q10 $q9_q10_q11 $q10_q11_q12 $q11_q12_q13 $q12_q13_q14 $q13_q14_q15 $q14_q15_q16 $q15_q16_q17 $q16_q17_q18 $q17_q18_q19 $q18_q19_q20 $q19_q20_q21 $q20_q21_q22 $q21_q22_q23 $q22_q23_q24 $q23_q24_q25 $q24_q25_q26 $q25_q26_q27 $q26_q27_q28 $q27_q28_q29 $q28_q29_q30 $q29_q30_q31 $q30_q31_q0 $q31_q0_q1 $x0_x1_x2_x3_x4_x5_x6_x7 $x2_x3_x4_x5_x6_x7_x8_x9 $x4_x5_x6_x7_x8_x9_x10_x11 $x6_x7_x8_x9_x10_x11_x12_x13 $x8_x9_x10_x11_x12_x13_x14_x15 $x10_x11_x12_x13_x14_x15_x16_x17 $x12_x13_x14_x15_x16_x17_x18_x19 $x14_x15_x16_x17_x18_x19_x20_x21 $x16_x17_x18_x19_x20_x21_x22_x23 $x18_x19_x20_x21_x22_x23_x24_x25 $w30_wzr $w0_w1 $w2_w3 $w4_w5 $w6_w7 $w8_w9 $w10_w11 $w12_w13 $w14_w15 $w16_w17 $w18_w19 $lr_xzr $x0_x1 $x2_x3 $x4_x5 $x6_x7 $x8_x9 $x10_x11 $x12_x13 $x14_x15 $x16_x17 $x18_x19 $z0_z1 $z1_z2 $z2_z3 $z3_z4 $z4_z5 $z5_z6 $z6_z7 $z7_z8 $z8_z9 $z9_z10 $z10_z11 $z11_z12 $z12_z13 $z13_z14 $z14_z15 $z15_z16 $z16_z17 $z17_z18 $z18_z19 $z19_z20 $z20_z21 $z21_z22 $z22_z23 $z23_z24 $z24_z25 $z25_z26 $z26_z27 $z27_z28 $z28_z29 $z29_z30 $z30_z31 $z31_z0 $z0_z1_z2_z3 $z1_z2_z3_z4 $z2_z3_z4_z5 $z3_z4_z5_z6 $z4_z5_z6_z7 $z5_z6_z7_z8 $z6_z7_z8_z9 $z7_z8_z9_z10 $z8_z9_z10_z11 $z9_z10_z11_z12 $z10_z11_z12_z13 $z11_z12_z13_z14 $z12_z13_z14_z15 $z13_z14_z15_z16 $z14_z15_z16_z17 $z15_z16_z17_z18 $z16_z17_z18_z19 $z17_z18_z19_z20 $z18_z19_z20_z21 $z19_z20_z21_z22 $z20_z21_z22_z23 $z21_z22_z23_z24 $z22_z23_z24_z25 $z23_z24_z25_z26 $z24_z25_z26_z27 $z25_z26_z27_z28 $z26_z27_z28_z29 $z27_z28_z29_z30 $z28_z29_z30_z31 $z29_z30_z31_z0 $z30_z31_z0_z1 $z31_z0_z1_z2 $z0_z1_z2 $z1_z2_z3 $z2_z3_z4 $z3_z4_z5 $z4_z5_z6 $z5_z6_z7 $z6_z7_z8 $z7_z8_z9 $z8_z9_z10 $z9_z10_z11 $z10_z11_z12 $z11_z12_z13 $z12_z13_z14 $z13_z14_z15 $z14_z15_z16 $z15_z16_z17 $z16_z17_z18 $z17_z18_z19 $z18_z19_z20 $z19_z20_z21 $z20_z21_z22 $z21_z22_z23 $z22_z23_z24 $z23_z24_z25 $z24_z25_z26 $z25_z26_z27 $z26_z27_z28 $z27_z28_z29 $z28_z29_z30 $z29_z30_z31 $z30_z31_z0 $z31_z0_z1 $z16_z24 $z17_z25 $z18_z26 $z19_z27 $z20_z28 $z21_z29 $z22_z30 $z23_z31 $z0_z8 $z1_z9 $z2_z10 $z3_z11 $z4_z12 $z5_z13 $z6_z14 $z7_z15 $z16_z20_z24_z28 $z17_z21_z25_z29 $z18_z22_z26_z30 $z19_z23_z27_z31 $z0_z4_z8_z12 $z1_z5_z9_z13 $z2_z6_z10_z14 $z3_z7_z11_z15
+; CHECK: baz Clobbered Registers: $ffr $fpcr $fpmr $fpsr $nzcv $sp $vg $wsp $wsp_hi $za $b0 $b1 $b2 $b3 $b4 $b5 $b6 $b7 $b16 $b17 $b18 $b19 $b20 $b21 $b22 $b23 $b24 $b25 $b26 $b27 $b28 $b29 $b30 $b31 $d0 $d1 $d2 $d3 $d4 $d5 $d6 $d7 $d16 $d17 $d18 $d19 $d20 $d21 $d22 $d23 $d24 $d25 $d26 $d27 $d28 $d29 $d30 $d31 $h0 $h1 $h2 $h3 $h4 $h5 $h6 $h7 $h16 $h17 $h18 $h19 $h20 $h21 $h22 $h23 $h24 $h25 $h26 $h27 $h28 $h29 $h30 $h31 $p0 $p1 $p2 $p3 $p4 $p5 $p6 $p7 $p8 $p9 $p10 $p11 $p12 $p13 $p14 $p15 $pn0 $pn1 $pn2 $pn3 $pn4 $pn5 $pn6 $pn7 $pn8 $pn9 $pn10 $pn11 $pn12 $pn13 $pn14 $pn15 $q0 $q1 $q2 $q3 $q4 $q5 $q6 $q7 $q8 $q9 $q10 $q11 $q12 $q13 $q14 $q15 $q16 $q17 $q18 $q19 $q20 $q21 $q22 $q23 $q24 $q25 $q26 $q27 $q28 $q29 $q30 $q31 $s0 $s1 $s2 $s3 $s4 $s5 $s6 $s7 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 $s28 $s29 $s30 $s31 $w0 $w1 $w2 $w3 $w4 $w5 $w6 $w7 $w8 $w16 $w17 $w18 $x0 $x1 $x2 $x3 $x4 $x5 $x6 $x7 $x8 $x16 $x17 $x18 $z0 $z1 $z2 $z3 $z4 $z5 $z6 $z7 $z8 $z9 $z10 $z11 $z12 $z13 $z14 $z15 $z16 $z17 $z18 $z19 $z20 $z21 $z22 $z23 $z24 $z25 $z26 $z27 $z28 $z29 $z30 $z31 $zab0 $zad0 $zad1 $zad2 $zad3 $zad4 $zad5 $zad6 $zad7 $zah0 $zah1 $zaq0 $zaq1 $zaq2 $zaq3 $zaq4 $zaq5 $zaq6 $zaq7 $zaq8 $zaq9 $zaq10 $zaq11 $zaq12 $zaq13 $zaq14 $zaq15 $zas0 $zas1 $zas2 $zas3 $zt0 $b0_hi $b1_hi $b2_hi $b3_hi $b4_hi $b5_hi $b6_hi $b7_hi $b16_hi $b17_hi $b18_hi $b19_hi $b20_hi $b21_hi $b22_hi $b23_hi $b24_hi $b25_hi $b26_hi $b27_hi $b28_hi $b29_hi $b30_hi $b31_hi $d0_hi $d1_hi $d2_hi $d3_hi $d4_hi $d5_hi $d6_hi $d7_hi $d8_hi $d9_hi $d10_hi $d11_hi $d12_hi $d13_hi $d14_hi $d15_hi $d16_hi $d17_hi $d18_hi $d19_hi $d20_hi $d21_hi $d22_hi $d23_hi $d24_hi $d25_hi $d26_hi $d27_hi $d28_hi $d29_hi $d30_hi $d31_hi $h0_hi $h1_hi $h2_hi $h3_hi $h4_hi $h5_hi $h6_hi $h7_hi $h16_hi $h17_hi $h18_hi $h19_hi $h20_hi $h21_hi $h22_hi $h23_hi $h24_hi $h25_hi $h26_hi $h27_hi $h28_hi $h29_hi $h30_hi $h31_hi $q0_hi $q1_hi $q2_hi $q3_hi $q4_hi $q5_hi $q6_hi $q7_hi $q8_hi $q9_hi $q10_hi $q11_hi $q12_hi $q13_hi $q14_hi $q15_hi $q16_hi $q17_hi $q18_hi $q19_hi $q20_hi $q21_hi $q22_hi $q23_hi $q24_hi $q25_hi $q26_hi $q27_hi $q28_hi $q29_hi $q30_hi $q31_hi $s0_hi $s1_hi $s2_hi $s3_hi $s4_hi $s5_hi $s6_hi $s7_hi $s16_hi $s17_hi $s18_hi $s19_hi $s20_hi $s21_hi $s22_hi $s23_hi $s24_hi $s25_hi $s26_hi $s27_hi $s28_hi $s29_hi $s30_hi $s31_hi $w0_hi $w1_hi $w2_hi $w3_hi $w4_hi $w5_hi $w6_hi $w7_hi $w8_hi $w16_hi $w17_hi $w18_hi $d0_d1 $d1_d2 $d2_d3 $d3_d4 $d4_d5 $d5_d6 $d6_d7 $d7_d8 $d15_d16 $d16_d17 $d17_d18 $d18_d19 $d19_d20 $d20_d21 $d21_d22 $d22_d23 $d23_d24 $d24_d25 $d25_d26 $d26_d27 $d27_d28 $d28_d29 $d29_d30 $d30_d31 $d31_d0 $d0_d1_d2_d3 $d1_d2_d3_d4 $d2_d3_d4_d5 $d3_d4_d5_d6 $d4_d5_d6_d7 $d5_d6_d7_d8 $d6_d7_d8_d9 $d7_d8_d9_d10 $d13_d14_d15_d16 $d14_d15_d16_d17 $d15_d16_d17_d18 $d16_d17_d18_d19 $d17_d18_d19_d20 $d18_d19_d20_d21 $d19_d20_d21_d22 $d20_d21_d22_d23 $d21_d22_d23_d24 $d22_d23_d24_d25 $d23_d24_d25_d26 $d24_d25_d26_d27 $d25_d26_d27_d28 $d26_d27_d28_d29 $d27_d28_d29_d30 $d28_d29_d30_d31 $d29_d30_d31_d0 $d30_d31_d0_d1 $d31_d0_d1_d2 $d0_d1_d2 $d1_d2_d3 $d2_d3_d4 $d3_d4_d5 $d4_d5_d6 $d5_d6_d7 $d6_d7_d8 $d7_d8_d9 $d14_d15_d16 $d15_d16_d17 $d16_d17_d18 $d17_d18_d19 $d18_d19_d20 $d19_d20_d21 $d20_d21_d22 $d21_d22_d23 $d22_d23_d24 $d23_d24_d25 $d24_d25_d26 $d25_d26_d27 $d26_d27_d28 $d27_d28_d29 $d28_d29_d30 $d29_d30_d31 $d30_d31_d0 $d31_d0_d1 $p0_p1 $p1_p2 $p2_p3 $p3_p4 $p4_p5 $p5_p6 $p6_p7 $p7_p8 $p8_p9 $p9_p10 $p10_p11 $p11_p12 $p12_p13 $p13_p14 $p14_p15 $p15_p0 $q0_q1 $q1_q2 $q2_q3 $q3_q4 $q4_q5 $q5_q6 $q6_q7 $q7_q8 $q8_q9 $q9_q10 $q10_q11 $q11_q12 $q12_q13 $q13_q14 $q14_q15 $q15_q16 $q16_q17 $q17_q18 $q18_q19 $q19_q20 $q20_q21 $q21_q22 $q22_q23 $q23_q24 $q24_q25 $q25_q26 $q26_q27 $q27_q28 $q28_q29 $q29_q30 $q30_q31 $q31_q0 $q0_q1_q2_q3 $q1_q2_q3_q4 $q2_q3_q4_q5 $q3_q4_q5_q6 $q4_q5_q6_q7 $q5_q6_q7_q8 $q6_q7_q8_q9 $q7_q8_q9_q10 $q8_q9_q10_q11 $q9_q10_q11_q12 $q10_q11_q12_q13 $q11_q12_q13_q14 $q12_q13_q14_q15 $q13_q14_q15_q16 $q14_q15_q16_q17 $q15_q16_q17_q18 $q16_q17_q18_q19 $q17_q18_q19_q20 $q18_q19_q20_q21 $q19_q20_q21_q22 $q20_q21_q22_q23 $q21_q22_q23_q24 $q22_q23_q24_q25 $q23_q24_q25_q26 $q24_q25_q26_q27 $q25_q26_q27_q28 $q26_q27_q28_q29 $q27_q28_q29_q30 $q28_q29_q30_q31 $q29_q30_q31_q0 $q30_q31_q0_q1 $q31_q0_q1_q2 $q0_q1_q2 $q1_q2_q3 $q2_q3_q4 $q3_q4_q5 $q4_q5_q6 $q5_q6_q7 $q6_q7_q8 $q7_q8_q9 $q8_q9_q10 $q9_q10_q11 $q10_q11_q12 $q11_q12_q13 $q12_q13_q14 $q13_q14_q15 $q14_q15_q16 $q15_q16_q17 $q16_q17_q18 $q17_q18_q19 $q18_q19_q20 $q19_q20_q21 $q20_q21_q22 $q21_q22_q23 $q22_q23_q24 $q23_q24_q25 $q24_q25_q26 $q25_q26_q27 $q26_q27_q28 $q27_q28_q29 $q28_q29_q30 $q29_q30_q31 $q30_q31_q0 $q31_q0_q1 $x0_x1_x2_x3_x4_x5_x6_x7 $x2_x3_x4_x5_x6_x7_x8_x9 $x4_x5_x6_x7_x8_x9_x10_x11 $x6_x7_x8_x9_x10_x11_x12_x13 $x8_x9_x10_x11_x12_x13_x14_x15 $x10_x11_x12_x13_x14_x15_x16_x17 $x12_x13_x14_x15_x16_x17_x18_x19 $x14_x15_x16_x17_x18_x19_x20_x21 $x16_x17_x18_x19_x20_x21_x22_x23 $x18_x19_x20_x21_x22_x23_x24_x25 $w30_wzr $w0_w1 $w2_w3 $w4_w5 $w6_w7 $w8_w9 $w10_w11 $w12_w13 $w14_w15 $w16_w17 $w18_w19 $lr_xzr $x0_x1 $x2_x3 $x4_x5 $x6_x7 $x8_x9 $x10_x11 $x12_x13 $x14_x15 $x16_x17 $x18_x19 $z0_z1 $z1_z2 $z2_z3 $z3_z4 $z4_z5 $z5_z6 $z6_z7 $z7_z8 $z8_z9 $z9_z10 $z10_z11 $z11_z12 $z12_z13 $z13_z14 $z14_z15 $z15_z16 $z16_z17 $z17_z18 $z18_z19 $z19_z20 $z20_z21 $z21_z22 $z22_z23 $z23_z24 $z24_z25 $z25_z26 $z26_z27 $z27_z28 $z28_z29 $z29_z30 $z30_z31 $z31_z0 $z0_z1_z2_z3 $z1_z2_z3_z4 $z2_z3_z4_z5 $z3_z4_z5_z6 $z4_z5_z6_z7 $z5_z6_z7_z8 $z6_z7_z8_z9 $z7_z8_z9_z10 $z8_z9_z10_z11 $z9_z10_z11_z12 $z10_z11_z12_z13 $z11_z12_z13_z14 $z12_z13_z14_z15 $z13_z14_z15_z16 $z14_z15_z16_z17 $z15_z16_z17_z18 $z16_z17_z18_z19 $z17_z18_z19_z20 $z18_z19_z20_z21 $z19_z20_z21_z22 $z20_z21_z22_z23 $z21_z22_z23_z24 $z22_z23_z24_z25 $z23_z24_z25_z26 $z24_z25_z26_z27 $z25_z26_z27_z28 $z26_z27_z28_z29 $z27_z28_z29_z30 $z28_z29_z30_z31 $z29_z30_z31_z0 $z30_z31_z0_z1 $z31_z0_z1_z2 $z0_z1_z2 $z1_z2_z3 $z2_z3_z4 $z3_z4_z5 $z4_z5_z6 $z5_z6_z7 $z6_z7_z8 $z7_z8_z9 $z8_z9_z10 $z9_z10_z11 $z10_z11_z12 $z11_z12_z13 $z12_z13_z14 $z13_z14_z15 $z14_z15_z16 $z15_z16_z17 $z16_z17_z18 $z17_z18_z19 $z18_z19_z20 $z19_z20_z21 $z20_z21_z22 $z21_z22_z23 $z22_z23_z24 $z23_z24_z25 $z24_z25_z26 $z25_z26_z27 $z26_z27_z28 $z27_z28_z29 $z28_z29_z30 $z29_z30_z31 $z30_z31_z0 $z31_z0_z1 $z16_z24 $z17_z25 $z18_z26 $z19_z27 $z20_z28 $z21_z29 $z22_z30 $z23_z31 $z0_z8 $z1_z9 $z2_z10 $z3_z11 $z4_z12 $z5_z13 $z6_z14 $z7_z15 $z16_z20_z24_z28 $z17_z21_z25_z29 $z18_z22_z26_z30 $z19_z23_z27_z31 $z0_z4_z8_z12 $z1_z5_z9_z13 $z2_z6_z10_z14 $z3_z7_z11_z15
call void @bar1()
call void @bar2()
ret void
}
define preserve_allcc void @foo() #0 {
-; CHECK: foo Clobbered Registers: $ffr $fpcr $fpmr $fpsr $nzcv $sp $vg $wsp $za $b0 $b1 $b2 $b3 $b4 $b5 $b6 $b7 $d0 $d1 $d2 $d3 $d4 $d5 $d6 $d7 $h0 $h1 $h2 $h3 $h4 $h5 $h6 $h7 $p0 $p1 $p2 $p3 $p4 $p5 $p6 $p7 $p8 $p9 $p10 $p11 $p12 $p13 $p14 $p15 $pn0 $pn1 $pn2 $pn3 $pn4 $pn5 $pn6 $pn7 $pn8 $pn9 $pn10 $pn11 $pn12 $pn13 $pn14 $pn15 $q0 $q1 $q2 $q3 $q4 $q5 $q6 $q7 $s0 $s1 $s2 $s3 $s4 $s5 $s6 $s7 $w0 $w1 $w2 $w3 $w4 $w5 $w6 $w7 $w8 $w16 $w17 $w18 $x0 $x1 $x2 $x3 $x4 $x5 $x6 $x7 $x8 $x16 $x17 $x18 $z0 $z1 $z2 $z3 $z4 $z5 $z6 $z7 $z8 $z9 $z10 $z11 $z12 $z13 $z14 $z15 $z16 $z17 $z18 $z19 $z20 $z21 $z22 $z23 $z24 $z25 $z26 $z27 $z28 $z29 $z30 $z31 $zab0 $zad0 $zad1 $zad2 $zad3 $zad4 $zad5 $zad6 $zad7 $zah0 $zah1 $zaq0 $zaq1 $zaq2 $zaq3 $zaq4 $zaq5 $zaq6 $zaq7 $zaq8 $zaq9 $zaq10 $zaq11 $zaq12 $zaq13 $zaq14 $zaq15 $zas0 $zas1 $zas2 $zas3 $zt0 $d0_d1 $d1_d2 $d2_d3 $d3_d4 $d4_d5 $d5_d6 $d6_d7 $d7_d8 $d15_d16 $d16_d17 $d17_d18 $d18_d19 $d19_d20 $d20_d21 $d21_d22 $d22_d23 $d23_d24 $d24_d25 $d25_d26 $d26_d27 $d27_d28 $d28_d29 $d29_d30 $d30_d31 $d31_d0 $d0_d1_d2_d3 $d1_d2_d3_d4 $d2_d3_d4_d5 $d3_d4_d5_d6 $d4_d5_d6_d7 $d5_d6_d7_d8 $d6_d7_d8_d9 $d7_d8_d9_d10 $d13_d14_d15_d16 $d14_d15_d16_d17 $d15_d16_d17_d18 $d16_d17_d18_d19 $d17_d18_d19_d20 $d18_d19_d20_d21 $d19_d20_d21_d22 $d20_d21_d22_d23 $d21_d22_d23_d24 $d22_d23_d24_d25 $d23_d24_d25_d26 $d24_d25_d26_d27 $d25_d26_d27_d28 $d26_d27_d28_d29 $d27_d28_d29_d30 $d28_d29_d30_d31 $d29_d30_d31_d0 $d30_d31_d0_d1 $d31_d0_d1_d2 $d0_d1_d2 $d1_d2_d3 $d2_d3_d4 $d3_d4_d5 $d4_d5_d6 $d5_d6_d7 $d6_d7_d8 $d7_d8_d9 $d14_d15_d16 $d15_d16_d17 $d16_d17_d18 $d17_d18_d19 $d18_d19_d20 $d19_d20_d21 $d20_d21_d22 $d21_d22_d23 $d22_d23_d24 $d23_d24_d25 $d24_d25_d26 $d25_d26_d27 $d26_d27_d28 $d27_d28_d29 $d28_d29_d30 $d29_d30_d31 $d30_d31_d0 $d31_d0_d1 $p0_p1 $p1_p2 $p2_p3 $p3_p4 $p4_p5 $p5_p6 $p6_p7 $p7_p8 $p8_p9 $p9_p10 $p10_p11 $p11_p12 $p12_p13 $p13_p14 $p14_p15 $p15_p0 $q0_q1 $q1_q2 $q2_q3 $q3_q4 $q4_q5 $q5_q6 $q6_q7 $q7_q8 $q8_q9 $q9_q10 $q10_q11 $q11_q12 $q12_q13 $q13_q14 $q14_q15 $q15_q16 $q16_q17 $q17_q18 $q18_q19 $q19_q20 $q20_q21 $q21_q22 $q22_q23 $q23_q24 $q24_q25 $q25_q26 $q26_q27 $q27_q28 $q28_q29 $q29_q30 $q30_q31 $q31_q0 $q0_q1_q2_q3 $q1_q2_q3_q4 $q2_q3_q4_q5 $q3_q4_q5_q6 $q4_q5_q6_q7 $q5_q6_q7_q8 $q6_q7_q8_q9 $q7_q8_q9_q10 $q8_q9_q10_q11 $q9_q10_q11_q12 $q10_q11_q12_q13 $q11_q12_q13_q14 $q12_q13_q14_q15 $q13_q14_q15_q16 $q14_q15_q16_q17 $q15_q16_q17_q18 $q16_q17_q18_q19 $q17_q18_q19_q20 $q18_q19_q20_q21 $q19_q20_q21_q22 $q20_q21_q22_q23 $q21_q22_q23_q24 $q22_q23_q24_q25 $q23_q24_q25_q26 $q24_q25_q26_q27 $q25_q26_q27_q28 $q26_q27_q28_q29 $q27_q28_q29_q30 $q28_q29_q30_q31 $q29_q30_q31_q0 $q30_q31_q0_q1 $q31_q0_q1_q2 $q0_q1_q2 $q1_q2_q3 $q2_q3_q4 $q3_q4_q5 $q4_q5_q6 $q5_q6_q7 $q6_q7_q8 $q7_q8_q9 $q8_q9_q10 $q9_q10_q11 $q10_q11_q12 $q11_q12_q13 $q12_q13_q14 $q13_q14_q15 $q14_q15_q16 $q15_q16_q17 $q16_q17_q18 $q17_q18_q19 $q18_q19_q20 $q19_q20_q21 $q20_q21_q22 $q21_q22_q23 $q22_q23_q24 $q23_q24_q25 $q24_q25_q26 $q25_q26_q27 $q26_q27_q28 $q27_q28_q29 $q28_q29_q30 $q29_q30_q31 $q30_q31_q0 $q31_q0_q1 $x0_x1_x2_x3_x4_x5_x6_x7 $x2_x3_x4_x5_x6_x7_x8_x9 $x4_x5_x6_x7_x8_x9_x10_x11 $x6_x7_x8_x9_x10_x11_x12_x13 $x8_x9_x10_x11_x12_x13_x14_x15 $x10_x11_x12_x13_x14_x15_x16_x17 $x12_x13_x14_x15_x16_x17_x18_x19 $x14_x15_x16_x17_x18_x19_x20_x21 $x16_x17_x18_x19_x20_x21_x22_x23 $x18_x19_x20_x21_x22_x23_x24_x25 $w30_wzr $w0_w1 $w2_w3 $w4_w5 $w6_w7 $w8_w9 $w10_w11 $w12_w13 $w14_w15 $w16_w17 $w18_w19 $lr_xzr $x0_x1 $x2_x3 $x4_x5 $x6_x7 $x8_x9 $x10_x11 $x12_x13 $x14_x15 $x16_x17 $x18_x19 $z0_z1 $z1_z2 $z2_z3 $z3_z4 $z4_z5 $z5_z6 $z6_z7 $z7_z8 $z8_z9 $z9_z10 $z10_z11 $z11_z12 $z12_z13 $z13_z14 $z14_z15 $z15_z16 $z16_z17 $z17_z18 $z18_z19 $z19_z20 $z20_z21 $z21_z22 $z22_z23 $z23_z24 $z24_z25 $z25_z26 $z26_z27 $z27_z28 $z28_z29 $z29_z30 $z30_z31 $z31_z0 $z0_z1_z2_z3 $z1_z2_z3_z4 $z2_z3_z4_z5 $z3_z4_z5_z6 $z4_z5_z6_z7 $z5_z6_z7_z8 $z6_z7_z8_z9 $z7_z8_z9_z10 $z8_z9_z10_z11 $z9_z10_z11_z12 $z10_z11_z12_z13 $z11_z12_z13_z14 $z12_z13_z14_z15 $z13_z14_z15_z16 $z14_z15_z16_z17 $z15_z16_z17_z18 $z16_z17_z18_z19 $z17_z18_z19_z20 $z18_z19_z20_z21 $z19_z20_z21_z22 $z20_z21_z22_z23 $z21_z22_z23_z24 $z22_z23_z24_z25 $z23_z24_z25_z26 $z24_z25_z26_z27 $z25_z26_z27_z28 $z26_z27_z28_z29 $z27_z28_z29_z30 $z28_z29_z30_z31 $z29_z30_z31_z0 $z30_z31_z0_z1 $z31_z0_z1_z2 $z0_z1_z2 $z1_z2_z3 $z2_z3_z4 $z3_z4_z5 $z4_z5_z6 $z5_z6_z7 $z6_z7_z8 $z7_z8_z9 $z8_z9_z10 $z9_z10_z11 $z10_z11_z12 $z11_z12_z13 $z12_z13_z14 $z13_z14_z15 $z14_z15_z16 $z15_z16_z17 $z16_z17_z18 $z17_z18_z19 $z18_z19_z20 $z19_z20_z21 $z20_z21_z22 $z21_z22_z23 $z22_z23_z24 $z23_z24_z25 $z24_z25_z26 $z25_z26_z27 $z26_z27_z28 $z27_z28_z29 $z28_z29_z30 $z29_z30_z31 $z30_z31_z0 $z31_z0_z1 $z16_z24 $z17_z25 $z18_z26 $z19_z27 $z20_z28 $z21_z29 $z22_z30 $z23_z31 $z0_z8 $z1_z9 $z2_z10 $z3_z11 $z4_z12 $z5_z13 $z6_z14 $z7_z15 $z16_z20_z24_z28 $z17_z21_z25_z29 $z18_z22_z26_z30 $z19_z23_z27_z31 $z0_z4_z8_z12 $z1_z5_z9_z13 $z2_z6_z10_z14 $z3_z7_z11_z15
+; CHECK: foo Clobbered Registers: $ffr $fpcr $fpmr $fpsr $nzcv $sp $vg $wsp $wsp_hi $za $b0 $b1 $b2 $b3 $b4 $b5 $b6 $b7 $d0 $d1 $d2 $d3 $d4 $d5 $d6 $d7 $h0 $h1 $h2 $h3 $h4 $h5 $h6 $h7 $p0 $p1 $p2 $p3 $p4 $p5 $p6 $p7 $p8 $p9 $p10 $p11 $p12 $p13 $p14 $p15 $pn0 $pn1 $pn2 $pn3 $pn4 $pn5 $pn6 $pn7 $pn8 $pn9 $pn10 $pn11 $pn12 $pn13 $pn14 $pn15 $q0 $q1 $q2 $q3 $q4 $q5 $q6 $q7 $s0 $s1 $s2 $s3 $s4 $s5 $s6 $s7 $w0 $w1 $w2 $w3 $w4 $w5 $w6 $w7 $w8 $w16 $w17 $w18 $x0 $x1 $x2 $x3 $x4 $x5 $x6 $x7 $x8 $x16 $x17 $x18 $z0 $z1 $z2 $z3 $z4 $z5 $z6 $z7 $z8 $z9 $z10 $z11 $z12 $z13 $z14 $z15 $z16 $z17 $z18 $z19 $z20 $z21 $z22 $z23 $z24 $z25 $z26 $z27 $z28 $z29 $z30 $z31 $zab0 $zad0 $zad1 $zad2 $zad3 $zad4 $zad5 $zad6 $zad7 $zah0 $zah1 $zaq0 $zaq1 $zaq2 $zaq3 $zaq4 $zaq5 $zaq6 $zaq7 $zaq8 $zaq9 $zaq10 $zaq11 $zaq12 $zaq13 $zaq14 $zaq15 $zas0 $zas1 $zas2 $zas3 $zt0 $b0_hi $b1_hi $b2_hi $b3_hi $b4_hi $b5_hi $b6_hi $b7_hi $d0_hi $d1_hi $d2_hi $d3_hi $d4_hi $d5_hi $d6_hi $d7_hi $h0_hi $h1_hi $h2_hi $h3_hi $h4_hi $h5_hi $h6_hi $h7_hi $q0_hi $q1_hi $q2_hi $q3_hi $q4_hi $q5_hi $q6_hi $q7_hi $q8_hi $q9_hi $q10_hi $q11_hi $q12_hi $q13_hi $q14_hi $q15_hi $q16_hi $q17_hi $q18_hi $q19_hi $q20_hi $q21_hi $q22_hi $q23_hi $q24_hi $q25_hi $q26_hi $q27_hi $q28_hi $q29_hi $q30_hi $q31_hi $s0_hi $s1_hi $s2_hi $s3_hi $s4_hi $s5_hi $s6_hi $s7_hi $w0_hi $w1_hi $w2_hi $w3_hi $w4_hi $w5_hi $w6_hi $w7_hi $w8_hi $w16_hi $w17_hi $w18_hi $d0_d1 $d1_d2 $d2_d3 $d3_d4 $d4_d5 $d5_d6 $d6_d7 $d7_d8 $d15_d16 $d16_d17 $d17_d18 $d18_d19 $d19_d20 $d20_d21 $d21_d22 $d22_d23 $d23_d24 $d24_d25 $d25_d26 $d26_d27 $d27_d28 $d28_d29 $d29_d30 $d30_d31 $d31_d0 $d0_d1_d2_d3 $d1_d2_d3_d4 $d2_d3_d4_d5 $d3_d4_d5_d6 $d4_d5_d6_d7 $d5_d6_d7_d8 $d6_d7_d8_d9 $d7_d8_d9_d10 $d13_d14_d15_d16 $d14_d15_d16_d17 $d15_d16_d17_d18 $d16_d17_d18_d19 $d17_d18_d19_d20 $d18_d19_d20_d21 $d19_d20_d21_d22 $d20_d21_d22_d23 $d21_d22_d23_d24 $d22_d23_d24_d25 $d23_d24_d25_d26 $d24_d25_d26_d27 $d25_d26_d27_d28 $d26_d27_d28_d29 $d27_d28_d29_d30 $d28_d29_d30_d31 $d29_d30_d31_d0 $d30_d31_d0_d1 $d31_d0_d1_d2 $d0_d1_d2 $d1_d2_d3 $d2_d3_d4 $d3_d4_d5 $d4_d5_d6 $d5_d6_d7 $d6_d7_d8 $d7_d8_d9 $d14_d15_d16 $d15_d16_d17 $d16_d17_d18 $d17_d18_d19 $d18_d19_d20 $d19_d20_d21 $d20_d21_d22 $d21_d22_d23 $d22_d23_d24 $d23_d24_d25 $d24_d25_d26 $d25_d26_d27 $d26_d27_d28 $d27_d28_d29 $d28_d29_d30 $d29_d30_d31 $d30_d31_d0 $d31_d0_d1 $p0_p1 $p1_p2 $p2_p3 $p3_p4 $p4_p5 $p5_p6 $p6_p7 $p7_p8 $p8_p9 $p9_p10 $p10_p11 $p11_p12 $p12_p13 $p13_p14 $p14_p15 $p15_p0 $q0_q1 $q1_q2 $q2_q3 $q3_q4 $q4_q5 $q5_q6 $q6_q7 $q7_q8 $q8_q9 $q9_q10 $q10_q11 $q11_q12 $q12_q13 $q13_q14 $q14_q15 $q15_q16 $q16_q17 $q17_q18 $q18_q19 $q19_q20 $q20_q21 $q21_q22 $q22_q23 $q23_q24 $q24_q25 $q25_q26 $q26_q27 $q27_q28 $q28_q29 $q29_q30 $q30_q31 $q31_q0 $q0_q1_q2_q3 $q1_q2_q3_q4 $q2_q3_q4_q5 $q3_q4_q5_q6 $q4_q5_q6_q7 $q5_q6_q7_q8 $q6_q7_q8_q9 $q7_q8_q9_q10 $q8_q9_q10_q11 $q9_q10_q11_q12 $q10_q11_q12_q13 $q11_q12_q13_q14 $q12_q13_q14_q15 $q13_q14_q15_q16 $q14_q15_q16_q17 $q15_q16_q17_q18 $q16_q17_q18_q19 $q17_q18_q19_q20 $q18_q19_q20_q21 $q19_q20_q21_q22 $q20_q21_q22_q23 $q21_q22_q23_q24 $q22_q23_q24_q25 $q23_q24_q25_q26 $q24_q25_q26_q27 $q25_q26_q27_q28 $q26_q27_q28_q29 $q27_q28_q29_q30 $q28_q29_q30_q31 $q29_q30_q31_q0 $q30_q31_q0_q1 $q31_q0_q1_q2 $q0_q1_q2 $q1_q2_q3 $q2_q3_q4 $q3_q4_q5 $q4_q5_q6 $q5_q6_q7 $q6_q7_q8 $q7_q8_q9 $q8_q9_q10 $q9_q10_q11 $q10_q11_q12 $q11_q12_q13 $q12_q13_q14 $q13_q14_q15 $q14_q15_q16 $q15_q16_q17 $q16_q17_q18 $q17_q18_q19 $q18_q19_q20 $q19_q20_q21 $q20_q21_q22 $q21_q22_q23 $q22_q23_q24 $q23_q24_q25 $q24_q25_q26 $q25_q26_q27 $q26_q27_q28 $q27_q28_q29 $q28_q29_q30 $q29_q30_q31 $q30_q31_q0 $q31_q0_q1 $x0_x1_x2_x3_x4_x5_x6_x7 $x2_x3_x4_x5_x6_x7_x8_x9 $x4_x5_x6_x7_x8_x9_x10_x11 $x6_x7_x8_x9_x10_x11_x12_x13 $x8_x9_x10_x11_x12_x13_x14_x15 $x10_x11_x12_x13_x14_x15_x16_x17 $x12_x13_x14_x15_x16_x17_x18_x19 $x14_x15_x16_x17_x18_x19_x20_x21 $x16_x17_x18_x19_x20_x21_x22_x23 $x18_x19_x20_x21_x22_x23_x24_x25 $w30_wzr $w0_w1 $w2_w3 $w4_w5 $w6_w7 $w8_w9 $w10_w11 $w12_w13 $w14_w15 $w16_w17 $w18_w19 $lr_xzr $x0_x1 $x2_x3 $x4_x5 $x6_x7 $x8_x9 $x10_x11 $x12_x13 $x14_x15 $x16_x17 $x18_x19 $z0_z1 $z1_z2 $z2_z3 $z3_z4 $z4_z5 $z5_z6 $z6_z7 $z7_z8 $z8_z9 $z9_z10 $z10_z11 $z11_z12 $z12_z13 $z13_z14 $z14_z15 $z15_z16 $z16_z17 $z17_z18 $z18_z19 $z19_z20 $z20_z21 $z21_z22 $z22_z23 $z23_z24 $z24_z25 $z25_z26 $z26_z27 $z27_z28 $z28_z29 $z29_z30 $z30_z31 $z31_z0 $z0_z1_z2_z3 $z1_z2_z3_z4 $z2_z3_z4_z5 $z3_z4_z5_z6 $z4_z5_z6_z7 $z5_z6_z7_z8 $z6_z7_z8_z9 $z7_z8_z9_z10 $z8_z9_z10_z11 $z9_z10_z11_z12 $z10_z11_z12_z13 $z11_z12_z13_z14 $z12_z13_z14_z15 $z13_z14_z15_z16 $z14_z15_z16_z17 $z15_z16_z17_z18 $z16_z17_z18_z19 $z17_z18_z19_z20 $z18_z19_z20_z21 $z19_z20_z21_z22 $z20_z21_z22_z23 $z21_z22_z23_z24 $z22_z23_z24_z25 $z23_z24_z25_z26 $z24_z25_z26_z27 $z25_z26_z27_z28 $z26_z27_z28_z29 $z27_z28_z29_z30 $z28_z29_z30_z31 $z29_z30_z31_z0 $z30_z31_z0_z1 $z31_z0_z1_z2 $z0_z1_z2 $z1_z2_z3 $z2_z3_z4 $z3_z4_z5 $z4_z5_z6 $z5_z6_z7 $z6_z7_z8 $z7_z8_z9 $z8_z9_z10 $z9_z10_z11 $z10_z11_z12 $z11_z12_z13 $z12_z13_z14 $z13_z14_z15 $z14_z15_z16 $z15_z16_z17 $z16_z17_z18 $z17_z18_z19 $z18_z19_z20 $z19_z20_z21 $z20_z21_z22 $z21_z22_z23 $z22_z23_z24 $z23_z24_z25 $z24_z25_z26 $z25_z26_z27 $z26_z27_z28 $z27_z28_z29 $z28_z29_z30 $z29_z30_z31 $z30_z31_z0 $z31_z0_z1 $z16_z24 $z17_z25 $z18_z26 $z19_z27 $z20_z28 $z21_z29 $z22_z30 $z23_z31 $z0_z8 $z1_z9 $z2_z10 $z3_z11 $z4_z12 $z5_z13 $z6_z14 $z7_z15 $z16_z20_z24_z28 $z17_z21_z25_z29 $z18_z22_z26_z30 $z19_z23_z27_z31 $z0_z4_z8_z12 $z1_z5_z9_z13 $z2_z6_z10_z14 $z3_z7_z11_z15
call void @bar1()
call void @bar2()
ret void
}
define preserve_nonecc void @qux() #0 {
-; CHECK: qux Clobbered Registers: $ffr $fpcr $fpmr $fpsr $nzcv $sp $vg $wsp $za $b0 $b1 $b2 $b3 $b4 $b5 $b6 $b7 $b16 $b17 $b18 $b19 $b20 $b21 $b22 $b23 $b24 $b25 $b26 $b27 $b28 $b29 $b30 $b31 $d0 $d1 $d2 $d3 $d4 $d5 $d6 $d7 $d16 $d17 $d18 $d19 $d20 $d21 $d22 $d23 $d24 $d25 $d26 $d27 $d28 $d29 $d30 $d31 $h0 $h1 $h2 $h3 $h4 $h5 $h6 $h7 $h16 $h17 $h18 $h19 $h20 $h21 $h22 $h23 $h24 $h25 $h26 $h27 $h28 $h29 $h30 $h31 $p0 $p1 $p2 $p3 $p4 $p5 $p6 $p7 $p8 $p9 $p10 $p11 $p12 $p13 $p14 $p15 $pn0 $pn1 $pn2 $pn3 $pn4 $pn5 $pn6 $pn7 $pn8 $pn9 $pn10 $pn11 $pn12 $pn13 $pn14 $pn15 $q0 $q1 $q2 $q3 $q4 $q5 $q6 $q7 $q8 $q9 $q10 $q11 $q12 $q13 $q14 $q15 $q16 $q17 $q18 $q19 $q20 $q21 $q22 $q23 $q24 $q25 $q26 $q27 $q28 $q29 $q30 $q31 $s0 $s1 $s2 $s3 $s4 $s5 $s6 $s7 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 $s28 $s29 $s30 $s31 $w0 $w1 $w2 $w3 $w4 $w5 $w6 $w7 $w8 $w9 $w10 $w11 $w12 $w13 $w14 $w15 $w16 $w17 $w18 $x0 $x1 $x2 $x3 $x4 $x5 $x6 $x7 $x8 $x9 $x10 $x11 $x12 $x13 $x14 $x15 $x16 $x17 $x18 $z0 $z1 $z2 $z3 $z4 $z5 $z6 $z7 $z8 $z9 $z10 $z11 $z12 $z13 $z14 $z15 $z16 $z17 $z18 $z19 $z20 $z21 $z22 $z23 $z24 $z25 $z26 $z27 $z28 $z29 $z30 $z31 $zab0 $zad0 $zad1 $zad2 $zad3 $zad4 $zad5 $zad6 $zad7 $zah0 $zah1 $zaq0 $zaq1 $zaq2 $zaq3 $zaq4 $zaq5 $zaq6 $zaq7 $zaq8 $zaq9 $zaq10 $zaq11 $zaq12 $zaq13 $zaq14 $zaq15 $zas0 $zas1 $zas2 $zas3 $zt0 $d0_d1 $d1_d2 $d2_d3 $d3_d4 $d4_d5 $d5_d6 $d6_d7 $d7_d8 $d15_d16 $d16_d17 $d17_d18 $d18_d19 $d19_d20 $d20_d21 $d21_d22 $d22_d23 $d23_d24 $d24_d25 $d25_d26 $d26_d27 $d27_d28 $d28_d29 $d29_d30 $d30_d31 $d31_d0 $d0_d1_d2_d3 $d1_d2_d3_d4 $d2_d3_d4_d5 $d3_d4_d5_d6 $d4_d5_d6_d7 $d5_d6_d7_d8 $d6_d7_d8_d9 $d7_d8_d9_d10 $d13_d14_d15_d16 $d14_d15_d16_d17 $d15_d16_d17_d18 $d16_d17_d18_d19 $d17_d18_d19_d20 $d18_d19_d20_d21 $d19_d20_d21_d22 $d20_d21_d22_d23 $d21_d22_d23_d24 $d22_d23_d24_d25 $d23_d24_d25_d26 $d24_d25_d26_d27 $d25_d26_d27_d28 $d26_d27_d28_d29 $d27_d28_d29_d30 $d28_d29_d30_d31 $d29_d30_d31_d0 $d30_d31_d0_d1 $d31_d0_d1_d2 $d0_d1_d2 $d1_d2_d3 $d2_d3_d4 $d3_d4_d5 $d4_d5_d6 $d5_d6_d7 $d6_d7_d8 $d7_d8_d9 $d14_d15_d16 $d15_d16_d17 $d16_d17_d18 $d17_d18_d19 $d18_d19_d20 $d19_d20_d21 $d20_d21_d22 $d21_d22_d23 $d22_d23_d24 $d23_d24_d25 $d24_d25_d26 $d25_d26_d27 $d26_d27_d28 $d27_d28_d29 $d28_d29_d30 $d29_d30_d31 $d30_d31_d0 $d31_d0_d1 $p0_p1 $p1_p2 $p2_p3 $p3_p4 $p4_p5 $p5_p6 $p6_p7 $p7_p8 $p8_p9 $p9_p10 $p10_p11 $p11_p12 $p12_p13 $p13_p14 $p14_p15 $p15_p0 $q0_q1 $q1_q2 $q2_q3 $q3_q4 $q4_q5 $q5_q6 $q6_q7 $q7_q8 $q8_q9 $q9_q10 $q10_q11 $q11_q12 $q12_q13 $q13_q14 $q14_q15 $q15_q16 $q16_q17 $q17_q18 $q18_q19 $q19_q20 $q20_q21 $q21_q22 $q22_q23 $q23_q24 $q24_q25 $q25_q26 $q26_q27 $q27_q28 $q28_q29 $q29_q30 $q30_q31 $q31_q0 $q0_q1_q2_q3 $q1_q2_q3_q4 $q2_q3_q4_q5 $q3_q4_q5_q6 $q4_q5_q6_q7 $q5_q6_q7_q8 $q6_q7_q8_q9 $q7_q8_q9_q10 $q8_q9_q10_q11 $q9_q10_q11_q12 $q10_q11_q12_q13 $q11_q12_q13_q14 $q12_q13_q14_q15 $q13_q14_q15_q16 $q14_q15_q16_q17 $q15_q16_q17_q18 $q16_q17_q18_q19 $q17_q18_q19_q20 $q18_q19_q20_q21 $q19_q20_q21_q22 $q20_q21_q22_q23 $q21_q22_q23_q24 $q22_q23_q24_q25 $q23_q24_q25_q26 $q24_q25_q26_q27 $q25_q26_q27_q28 $q26_q27_q28_q29 $q27_q28_q29_q30 $q28_q29_q30_q31 $q29_q30_q31_q0 $q30_q31_q0_q1 $q31_q0_q1_q2 $q0_q1_q2 $q1_q2_q3 $q2_q3_q4 $q3_q4_q5 $q4_q5_q6 $q5_q6_q7 $q6_q7_q8 $q7_q8_q9 $q8_q9_q10 $q9_q10_q11 $q10_q11_q12 $q11_q12_q13 $q12_q13_q14 $q13_q14_q15 $q14_q15_q16 $q15_q16_q17 $q16_q17_q18 $q17_q18_q19 $q18_q19_q20 $q19_q20_q21 $q20_q21_q22 $q21_q22_q23 $q22_q23_q24 $q23_q24_q25 $q24_q25_q26 $q25_q26_q27 $q26_q27_q28 $q27_q28_q29 $q28_q29_q30 $q29_q30_q31 $q30_q31_q0 $q31_q0_q1 $x0_x1_x2_x3_x4_x5_x6_x7 $x2_x3_x4_x5_x6_x7_x8_x9 $x4_x5_x6_x7_x8_x9_x10_x11 $x6_x7_x8_x9_x10_x11_x12_x13 $x8_x9_x10_x11_x12_x13_x14_x15 $x10_x11_x12_x13_x14_x15_x16_x17 $x12_x13_x14_x15_x16_x17_x18_x19 $x14_x15_x16_x17_x18_x19_x20_x21 $x16_x17_x18_x19_x20_x21_x22_x23 $x18_x19_x20_x21_x22_x23_x24_x25 $w30_wzr $w0_w1 $w2_w3 $w4_w5 $w6_w7 $w8_w9 $w10_w11 $w12_w13 $w14_w15 $w16_w17 $w18_w19 $lr_xzr $x0_x1 $x2_x3 $x4_x5 $x6_x7 $x8_x9 $x10_x11 $x12_x13 $x14_x15 $x16_x17 $x18_x19 $z0_z1 $z1_z2 $z2_z3 $z3_z4 $z4_z5 $z5_z6 $z6_z7 $z7_z8 $z8_z9 $z9_z10 $z10_z11 $z11_z12 $z12_z13 $z13_z14 $z14_z15 $z15_z16 $z16_z17 $z17_z18 $z18_z19 $z19_z20 $z20_z21 $z21_z22 $z22_z23 $z23_z24 $z24_z25 $z25_z26 $z26_z27 $z27_z28 $z28_z29 $z29_z30 $z30_z31 $z31_z0 $z0_z1_z2_z3 $z1_z2_z3_z4 $z2_z3_z4_z5 $z3_z4_z5_z6 $z4_z5_z6_z7 $z5_z6_z7_z8 $z6_z7_z8_z9 $z7_z8_z9_z10 $z8_z9_z10_z11 $z9_z10_z11_z12 $z10_z11_z12_z13 $z11_z12_z13_z14 $z12_z13_z14_z15 $z13_z14_z15_z16 $z14_z15_z16_z17 $z15_z16_z17_z18 $z16_z17_z18_z19 $z17_z18_z19_z20 $z18_z19_z20_z21 $z19_z20_z21_z22 $z20_z21_z22_z23 $z21_z22_z23_z24 $z22_z23_z24_z25 $z23_z24_z25_z26 $z24_z25_z26_z27 $z25_z26_z27_z28 $z26_z27_z28_z29 $z27_z28_z29_z30 $z28_z29_z30_z31 $z29_z30_z31_z0 $z30_z31_z0_z1 $z31_z0_z1_z2 $z0_z1_z2 $z1_z2_z3 $z2_z3_z4 $z3_z4_z5 $z4_z5_z6 $z5_z6_z7 $z6_z7_z8 $z7_z8_z9 $z8_z9_z10 $z9_z10_z11 $z10_z11_z12 $z11_z12_z13 $z12_z13_z14 $z13_z14_z15 $z14_z15_z16 $z15_z16_z17 $z16_z17_z18 $z17_z18_z19 $z18_z19_z20 $z19_z20_z21 $z20_z21_z22 $z21_z22_z23 $z22_z23_z24 $z23_z24_z25 $z24_z25_z26 $z25_z26_z27 $z26_z27_z28 $z27_z28_z29 $z28_z29_z30 $z29_z30_z31 $z30_z31_z0 $z31_z0_z1 $z16_z24 $z17_z25 $z18_z26 $z19_z27 $z20_z28 $z21_z29 $z22_z30 $z23_z31 $z0_z8 $z1_z9 $z2_z10 $z3_z11 $z4_z12 $z5_z13 $z6_z14 $z7_z15 $z16_z20_z24_z28 $z17_z21_z25_z29 $z18_z22_z26_z30 $z19_z23_z27_z31 $z0_z4_z8_z12 $z1_z5_z9_z13 $z2_z6_z10_z14 $z3_z7_z11_z15
-
+; CHECK: qux Clobbered Registers: $ffr $fpcr $fpmr $fpsr $nzcv $sp $vg $wsp $wsp_hi $za $b0 $b1 $b2 $b3 $b4 $b5 $b6 $b7 $b16 $b17 $b18 $b19 $b20 $b21 $b22 $b23 $b24 $b25 $b26 $b27 $b28 $b29 $b30 $b31 $d0 $d1 $d2 $d3 $d4 $d5 $d6 $d7 $d16 $d17 $d18 $d19 $d20 $d21 $d22 $d23 $d24 $d25 $d26 $d27 $d28 $d29 $d30 $d31 $h0 $h1 $h2 $h3 $h4 $h5 $h6 $h7 $h16 $h17 $h18 $h19 $h20 $h21 $h22 $h23 $h24 $h25 $h26 $h27 $h28 $h29 $h30 $h31 $p0 $p1 $p2 $p3 $p4 $p5 $p6 $p7 $p8 $p9 $p10 $p11 $p12 $p13 $p14 $p15 $pn0 $pn1 $pn2 $pn3 $pn4 $pn5 $pn6 $pn7 $pn8 $pn9 $pn10 $pn11 $pn12 $pn13 $pn14 $pn15 $q0 $q1 $q2 $q3 $q4 $q5 $q6 $q7 $q8 $q9 $q10 $q11 $q12 $q13 $q14 $q15 $q16 $q17 $q18 $q19 $q20 $q21 $q22 $q23 $q24 $q25 $q26 $q27 $q28 $q29 $q30 $q31 $s0 $s1 $s2 $s3 $s4 $s5 $s6 $s7 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 $s28 $s29 $s30 $s31 $w0 $w1 $w2 $w3 $w4 $w5 $w6 $w7 $w8 $w9 $w10 $w11 $w12 $w13 $w14 $w15 $w16 $w17 $w18 $x0 $x1 $x2 $x3 $x4 $x5 $x6 $x7 $x8 $x9 $x10 $x11 $x12 $x13 $x14 $x15 $x16 $x17 $x18 $z0 $z1 $z2 $z3 $z4 $z5 $z6 $z7 $z8 $z9 $z10 $z11 $z12 $z13 $z14 $z15 $z16 $z17 $z18 $z19 $z20 $z21 $z22 $z23 $z24 $z25 $z26 $z27 $z28 $z29 $z30 $z31 $zab0 $zad0 $zad1 $zad2 $zad3 $zad4 $zad5 $zad6 $zad7 $zah0 $zah1 $zaq0 $zaq1 $zaq2 $zaq3 $zaq4 $zaq5 $zaq6 $zaq7 $zaq8 $zaq9 $zaq10 $zaq11 $zaq12 $zaq13 $zaq14 $zaq15 $zas0 $zas1 $zas2 $zas3 $zt0 $b0_hi $b1_hi $b2_hi $b3_hi $b4_hi $b5_hi $b6_hi $b7_hi $b16_hi $b17_hi $b18_hi $b19_hi $b20_hi $b21_hi $b22_hi $b23_hi $b24_hi $b25_hi $b26_hi $b27_hi $b28_hi $b29_hi $b30_hi $b31_hi $d0_hi $d1_hi $d2_hi $d3_hi $d4_hi $d5_hi $d6_hi $d7_hi $d8_hi $d9_hi $d10_hi $d11_hi $d12_hi $d13_hi $d14_hi $d15_hi $d16_hi $d17_hi $d18_hi $d19_hi $d20_hi $d21_hi $d22_hi $d23_hi $d24_hi $d25_hi $d26_hi $d27_hi $d28_hi $d29_hi $d30_hi $d31_hi $h0_hi $h1_hi $h2_hi $h3_hi $h4_hi $h5_hi $h6_hi $h7_hi $h16_hi $h17_hi $h18_hi $h19_hi $h20_hi $h21_hi $h22_hi $h23_hi $h24_hi $h25_hi $h26_hi $h27_hi $h28_hi $h29_hi $h30_hi $h31_hi $q0_hi $q1_hi $q2_hi $q3_hi $q4_hi $q5_hi $q6_hi $q7_hi $q8_hi $q9_hi $q10_hi $q11_hi $q12_hi $q13_hi $q14_hi $q15_hi $q16_hi $q17_hi $q18_hi $q19_hi $q20_hi $q21_hi $q22_hi $q23_hi $q24_hi $q25_hi $q26_hi $q27_hi $q28_hi $q29_hi $q30_hi $q31_hi $s0_hi $s1_hi $s2_hi $s3_hi $s4_hi $s5_hi $s6_hi $s7_hi $s16_hi $s17_hi $s18_hi $s19_hi $s20_hi $s21_hi $s22_hi $s23_hi $s24_hi $s25_hi $s26_hi $s27_hi $s28_hi $s29_hi $s30_hi $s31_hi $w0_hi $w1_hi $w2_hi $w3_hi $w4_hi $w5_hi $w6_hi $w7_hi $w8_hi $w9_hi $w10_hi $w11_hi $w12_hi $w13_hi $w14_hi $w15_hi $w16_hi $w17_hi $w18_hi $d0_d1 $d1_d2 $d2_d3 $d3_d4 $d4_d5 $d5_d6 $d6_d7 $d7_d8 $d15_d16 $d16_d17 $d17_d18 $d18_d19 $d19_d20 $d20_d21 $d21_d22 $d22_d23 $d23_d24 $d24_d25 $d25_d26 $d26_d27 $d27_d28 $d28_d29 $d29_d30 $d30_d31 $d31_d0 $d0_d1_d2_d3 $d1_d2_d3_d4 $d2_d3_d4_d5 $d3_d4_d5_d6 $d4_d5_d6_d7 $d5_d6_d7_d8 $d6_d7_d8_d9 $d7_d8_d9_d10 $d13_d14_d15_d16 $d14_d15_d16_d17 $d15_d16_d17_d18 $d16_d17_d18_d19 $d17_d18_d19_d20 $d18_d19_d20_d21 $d19_d20_d21_d22 $d20_d21_d22_d23 $d21_d22_d23_d24 $d22_d23_d24_d25 $d23_d24_d25_d26 $d24_d25_d26_d27 $d25_d26_d27_d28 $d26_d27_d28_d29 $d27_d28_d29_d30 $d28_d29_d30_d31 $d29_d30_d31_d0 $d30_d31_d0_d1 $d31_d0_d1_d2 $d0_d1_d2 $d1_d2_d3 $d2_d3_d4 $d3_d4_d5 $d4_d5_d6 $d5_d6_d7 $d6_d7_d8 $d7_d8_d9 $d14_d15_d16 $d15_d16_d17 $d16_d17_d18 $d17_d18_d19 $d18_d19_d20 $d19_d20_d21 $d20_d21_d22 $d21_d22_d23 $d22_d23_d24 $d23_d24_d25 $d24_d25_d26 $d25_d26_d27 $d26_d27_d28 $d27_d28_d29 $d28_d29_d30 $d29_d30_d31 $d30_d31_d0 $d31_d0_d1 $p0_p1 $p1_p2 $p2_p3 $p3_p4 $p4_p5 $p5_p6 $p6_p7 $p7_p8 $p8_p9 $p9_p10 $p10_p11 $p11_p12 $p12_p13 $p13_p14 $p14_p15 $p15_p0 $q0_q1 $q1_q2 $q2_q3 $q3_q4 $q4_q5 $q5_q6 $q6_q7 $q7_q8 $q8_q9 $q9_q10 $q10_q11 $q11_q12 $q12_q13 $q13_q14 $q14_q15 $q15_q16 $q16_q17 $q17_q18 $q18_q19 $q19_q20 $q20_q21 $q21_q22 $q22_q23 $q23_q24 $q24_q25 $q25_q26 $q26_q27 $q27_q28 $q28_q29 $q29_q30 $q30_q31 $q31_q0 $q0_q1_q2_q3 $q1_q2_q3_q4 $q2_q3_q4_q5 $q3_q4_q5_q6 $q4_q5_q6_q7 $q5_q6_q7_q8 $q6_q7_q8_q9 $q7_q8_q9_q10 $q8_q9_q10_q11 $q9_q10_q11_q12 $q10_q11_q12_q13 $q11_q12_q13_q14 $q12_q13_q14_q15 $q13_q14_q15_q16 $q14_q15_q16_q17 $q15_q16_q17_q18 $q16_q17_q18_q19 $q17_q18_q19_q20 $q18_q19_q20_q21 $q19_q20_q21_q22 $q20_q21_q22_q23 $q21_q22_q23_q24 $q22_q23_q24_q25 $q23_q24_q25_q26 $q24_q25_q26_q27 $q25_q26_q27_q28 $q26_q27_q28_q29 $q27_q28_q29_q30 $q28_q29_q30_q31 $q29_q30_q31_q0 $q30_q31_q0_q1 $q31_q0_q1_q2 $q0_q1_q2 $q1_q2_q3 $q2_q3_q4 $q3_q4_q5 $q4_q5_q6 $q5_q6_q7 $q6_q7_q8 $q7_q8_q9 $q8_q9_q10 $q9_q10_q11 $q10_q11_q12 $q11_q12_q13 $q12_q13_q14 $q13_q14_q15 $q14_q15_q16 $q15_q16_q17 $q16_q17_q18 $q17_q18_q19 $q18_q19_q20 $q19_q20_q21 $q20_q21_q22 $q21_q22_q23 $q22_q23_q24 $q23_q24_q25 $q24_q25_q26 $q25_q26_q27 $q26_q27_q28 $q27_q28_q29 $q28_q29_q30 $q29_q30_q31 $q30_q31_q0 $q31_q0_q1 $x0_x1_x2_x3_x4_x5_x6_x7 $x2_x3_x4_x5_x6_x7_x8_x9 $x4_x5_x6_x7_x8_x9_x10_x11 $x6_x7_x8_x9_x10_x11_x12_x13 $x8_x9_x10_x11_x12_x13_x14_x15 $x10_x11_x12_x13_x14_x15_x16_x17 $x12_x13_x14_x15_x16_x17_x18_x19 $x14_x15_x16_x17_x18_x19_x20_x21 $x16_x17_x18_x19_x20_x21_x22_x23 $x18_x19_x20_x21_x22_x23_x24_x25 $w30_wzr $w0_w1 $w2_w3 $w4_w5 $w6_w7 $w8_w9 $w10_w11 $w12_w13 $w14_w15 $w16_w17 $w18_w19 $lr_xzr $x0_x1 $x2_x3 $x4_x5 $x6_x7 $x8_x9 $x10_x11 $x12_x13 $x14_x15 $x16_x17 $x18_x19 $z0_z1 $z1_z2 $z2_z3 $z3_z4 $z4_z5 $z5_z6 $z6_z7 $z7_z8 $z8_z9 $z9_z10 $z10_z11 $z11_z12 $z12_z13 $z13_z14 $z14_z15 $z15_z16 $z16_z17 $z17_z18 $z18_z19 $z19_z20 $z20_z21 $z21_z22 $z22_z23 $z23_z24 $z24_z25 $z25_z26 $z26_z27 $z27_z28 $z28_z29 $z29_z30 $z30_z31 $z31_z0 $z0_z1_z2_z3 $z1_z2_z3_z4 $z2_z3_z4_z5 $z3_z4_z5_z6 $z4_z5_z6_z7 $z5_z6_z7_z8 $z6_z7_z8_z9 $z7_z8_z9_z10 $z8_z9_z10_z11 $z9_z10_z11_z12 $z10_z11_z12_z13 $z11_z12_z13_z14 $z12_z13_z14_z15 $z13_z14_z15_z16 $z14_z15_z16_z17 $z15_z16_z17_z18 $z16_z17_z18_z19 $z17_z18_z19_z20 $z18_z19_z20_z21 $z19_z20_z21_z22 $z20_z21_z22_z23 $z21_z22_z23_z24 $z22_z23_z24_z25 $z23_z24_z25_z26 $z24_z25_z26_z27 $z25_z26_z27_z28 $z26_z27_z28_z29 $z27_z28_z29_z30 $z28_z29_z30_z31 $z29_z30_z31_z0 $z30_z31_z0_z1 $z31_z0_z1_z2 $z0_z1_z2 $z1_z2_z3 $z2_z3_z4 $z3_z4_z5 $z4_z5_z6 $z5_z6_z7 $z6_z7_z8 $z7_z8_z9 $z8_z9_z10 $z9_z10_z11 $z10_z11_z12 $z11_z12_z13 $z12_z13_z14 $z13_z14_z15 $z14_z15_z16 $z15_z16_z17 $z16_z17_z18 $z17_z18_z19 $z18_z19_z20 $z19_z20_z21 $z20_z21_z22 $z21_z22_z23 $z22_z23_z24 $z23_z24_z25 $z24_z25_z26 $z25_z26_z27 $z26_z27_z28 $z27_z28_z29 $z28_z29_z30 $z29_z30_z31 $z30_z31_z0 $z31_z0_z1 $z16_z24 $z17_z25 $z18_z26 $z19_z27 $z20_z28 $z21_z29 $z22_z30 $z23_z31 $z0_z8 $z1_z9 $z2_z10 $z3_z11 $z4_z12 $z5_z13 $z6_z14 $z7_z15 $z16_z20_z24_z28 $z17_z21_z25_z29 $z18_z22_z26_z30 $z19_z23_z27_z31 $z0_z4_z8_z12 $z1_z5_z9_z13 $z2_z6_z10_z14 $z3_z7_z11_z15
call void @bar1()
call void @bar2()
ret void
diff --git a/llvm/test/CodeGen/AArch64/strpre-str-merge.mir b/llvm/test/CodeGen/AArch64/strpre-str-merge.mir
index 722de6bb343e2b..5c1937e0d7753e 100644
--- a/llvm/test/CodeGen/AArch64/strpre-str-merge.mir
+++ b/llvm/test/CodeGen/AArch64/strpre-str-merge.mir
@@ -156,7 +156,7 @@ body: |
; CHECK-LABEL: name: 6-strqui-strqpre-no-merge
; CHECK: liveins: $q0, $q1, $x0
; CHECK: STRQui renamable $q1, renamable $x0, 1 :: (store (s128))
- ; CHECK: early-clobber renamable $x0 = STRQpre renamable $q0, renamable $x0, 48, implicit $w0 :: (store (s128))
+ ; CHECK: early-clobber renamable $x0 = STRQpre renamable $q0, renamable $x0, 48, implicit $w0, implicit $w0_hi :: (store (s128))
; CHECK: RET undef $lr, implicit $x0
STRQui killed renamable $q1, renamable $x0, 1 :: (store (s128))
early-clobber renamable $x0 = STRQpre killed renamable $q0, killed renamable $x0, 48 :: (store (s128))
@@ -235,7 +235,7 @@ body: |
liveins: $s0, $s1, $x0, $x1
; CHECK-LABEL: name: 9-strspre-strsui-mod-base-reg-no-merge
; CHECK: liveins: $s0, $s1, $x0, $x1
- ; CHECK: dead early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 12, implicit $w0 :: (store (s32))
+ ; CHECK: dead early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 12, implicit $w0, implicit $w0_hi :: (store (s32))
; CHECK: renamable $x0 = LDRXui renamable $x1, 1 :: (load (s64))
; CHECK: STRSui renamable $s1, renamable $x0, 1 :: (store (s32))
; CHECK: RET undef $lr, implicit $x0
@@ -265,7 +265,7 @@ body: |
liveins: $s0, $s1, $x0, $x1
; CHECK-LABEL: name: 10-strspre-strsui-used-base-reg-no-merge
; CHECK: liveins: $s0, $s1, $x0, $x1
- ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 12, implicit $w0 :: (store (s32))
+ ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 12, implicit $w0, implicit $w0_hi :: (store (s32))
; CHECK: STRXui renamable $x1, renamable $x1, 1 :: (store (s32))
; CHECK: STRSui renamable $s1, renamable $x0, 1 :: (store (s32))
; CHECK: RET undef $lr, implicit $x0
@@ -296,12 +296,12 @@ body: |
liveins: $s0, $s1, $x0
; CHECK-LABEL: name: 11-strspre-strspre-no-merge
; CHECK: liveins: $s0, $s1, $x0
- ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 12, implicit $w0 :: (store (s32))
- ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s1, renamable $x0, 16, implicit $w0 :: (store (s32))
- ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 4, implicit $w0 :: (store (s32))
- ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s1, renamable $x0, 12, implicit $w0 :: (store (s32))
- ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 4, implicit $w0 :: (store (s32))
- ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s1, renamable $x0, 4, implicit $w0 :: (store (s32))
+ ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 12, implicit $w0, implicit $w0_hi :: (store (s32))
+ ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s1, renamable $x0, 16, implicit $w0, implicit $w0_hi :: (store (s32))
+ ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 4, implicit $w0, implicit $w0_hi :: (store (s32))
+ ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s1, renamable $x0, 12, implicit $w0, implicit $w0_hi :: (store (s32))
+ ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 4, implicit $w0, implicit $w0_hi :: (store (s32))
+ ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s1, renamable $x0, 4, implicit $w0, implicit $w0_hi :: (store (s32))
; CHECK: RET undef $lr, implicit $x0
early-clobber renamable $x0 = STRSpre renamable $s0, killed renamable $x0, 12 :: (store (s32))
early-clobber renamable $x0 = STRSpre renamable $s1, killed renamable $x0, 16 :: (store (s32))
@@ -335,7 +335,7 @@ body: |
liveins: $s0, $s1, $x0
; CHECK-LABEL: name: 12-strspre-strsui-no-merge
; CHECK: liveins: $s0, $s1, $x0
- ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 12, implicit $w0 :: (store (s32))
+ ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 12, implicit $w0, implicit $w0_hi :: (store (s32))
; CHECK: STRSui renamable $s1, renamable $x0, 2 :: (store (s32))
; CHECK: RET undef $lr, implicit $x0
early-clobber renamable $x0 = STRSpre killed renamable $s0, killed renamable $x0, 12 :: (store (s32))
@@ -390,7 +390,7 @@ body: |
liveins: $q0, $q1, $x0
; CHECK-LABEL: name: 14-strqpre-sturqi-no-merge
; CHECK: liveins: $q0, $q1, $x0
- ; CHECK: early-clobber renamable $x0 = STRQpre renamable $q0, renamable $x0, 48, implicit $w0 :: (store (s128))
+ ; CHECK: early-clobber renamable $x0 = STRQpre renamable $q0, renamable $x0, 48, implicit $w0, implicit $w0_hi :: (store (s128))
; CHECK: STURQi renamable $q1, renamable $x0, 1 :: (store (s128))
; CHECK: RET undef $lr, implicit $x0
early-clobber renamable $x0 = STRQpre killed renamable $q0, killed renamable $x0, 48 :: (store (s128))
@@ -417,7 +417,7 @@ body: |
liveins: $s0, $s1, $x0
; CHECK-LABEL: name: 15-strspre-strsui-unaligned-no-merge
; CHECK: liveins: $s0, $s1, $x0
- ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 251, implicit $w0 :: (store (s32))
+ ; CHECK: early-clobber renamable $x0 = STRSpre renamable $s0, renamable $x0, 251, implicit $w0, implicit $w0_hi :: (store (s32))
; CHECK: STRSui renamable $s1, renamable $x0, 1 :: (store (s32))
; CHECK: RET undef $lr, implicit $x0
early-clobber renamable $x0 = STRSpre killed renamable $s0, killed renamable $x0, 251 :: (store (s32))
@@ -443,7 +443,7 @@ body: |
liveins: $x0, $x1, $x2
; CHECK-LABEL: name: 16-strxpre-strxui-same-reg-no-merge
; CHECK: liveins: $x0, $x1, $x2
- ; CHECK: early-clobber renamable $x0 = STRXpre renamable $x1, renamable $x0, 24, implicit $w0 :: (store (s64))
+ ; CHECK: early-clobber renamable $x0 = STRXpre renamable $x1, renamable $x0, 24, implicit $w0, implicit $w0_hi :: (store (s64))
; CHECK: STRXui renamable $x0, renamable $x0, 1 :: (store (s64))
; CHECK: RET undef $lr, implicit $x0
early-clobber renamable $x0 = STRXpre killed renamable $x1, killed renamable $x0, 24 :: (store (s64))
@@ -470,7 +470,7 @@ body: |
liveins: $x0, $x1, $x2
; CHECK-LABEL: name: 17-strwpre-strwui-same-reg-no-merge
; CHECK: liveins: $x0, $x1, $x2
- ; CHECK: early-clobber renamable $x0 = STRWpre renamable $w1, renamable $x0, 24, implicit $w0, implicit-def $w0 :: (store (s32))
+ ; CHECK: early-clobber renamable $x0 = STRWpre renamable $w1, renamable $x0, 24, implicit $w0, implicit $w0_hi, implicit-def $w0 :: (store (s32))
; CHECK: STRWui renamable $w0, renamable $x0, 1 :: (store (s32))
; CHECK: RET undef $lr, implicit $x0
early-clobber renamable $x0 = STRWpre killed renamable $w1, killed renamable $x0, 24 :: (store (s32))
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.mir b/llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.mir
index 45829b3198224d..f85658e9a596a0 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.mir
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-merging.mir
@@ -28,7 +28,7 @@ body: |
; CHECK-LABEL: name: bic_i16_zero
; CHECK: liveins: $p0, $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: BUNDLE implicit-def $z0, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $h0, implicit-def $b0, implicit killed $p0, implicit $z0 {
+ ; CHECK-NEXT: BUNDLE implicit-def $z0, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $h0, implicit-def $b0, implicit-def $b0_hi, implicit-def $h0_hi, implicit-def $s0_hi, implicit-def $d0_hi, implicit-def $q0_hi, implicit killed $p0, implicit $z0 {
; CHECK-NEXT: $z0 = MOVPRFX_ZPzZ_H $p0, $z0
; CHECK-NEXT: $z0 = LSL_ZPmI_H killed renamable $p0, internal $z0, 0
; CHECK-NEXT: $z0 = BIC_ZPmZ_H killed renamable $p0, internal killed $z0, internal killed renamable $z0
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryComm-merging.mir b/llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryComm-merging.mir
index 970077fdfea7b8..0e2f1c3ff4f697 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryComm-merging.mir
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryComm-merging.mir
@@ -28,7 +28,7 @@ body: |
; CHECK-LABEL: name: fmul_float_zero
; CHECK: liveins: $p0, $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: BUNDLE implicit-def $z0, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $h0, implicit-def $b0, implicit $p0, implicit $z0 {
+ ; CHECK-NEXT: BUNDLE implicit-def $z0, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $h0, implicit-def $b0, implicit-def $b0_hi, implicit-def $h0_hi, implicit-def $s0_hi, implicit-def $d0_hi, implicit-def $q0_hi, implicit $p0, implicit $z0 {
; CHECK-NEXT: $z0 = MOVPRFX_ZPzZ_S $p0, $z0
; CHECK-NEXT: $z0 = LSL_ZPmI_S renamable $p0, internal $z0, 0
; CHECK-NEXT: $z0 = FMUL_ZPmZ_S renamable $p0, internal killed $z0, internal killed renamable $z0
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryCommWithRev-merging.mir b/llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryCommWithRev-merging.mir
index 308291fb6fe933..548ebc26b83e80 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryCommWithRev-merging.mir
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-int-binaryCommWithRev-merging.mir
@@ -30,7 +30,7 @@ body: |
; CHECK-LABEL: name: fsub_s_zero
; CHECK: liveins: $p0, $z0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: BUNDLE implicit-def $z0, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $h0, implicit-def $b0, implicit $p0, implicit $z0 {
+ ; CHECK-NEXT: BUNDLE implicit-def $z0, implicit-def $q0, implicit-def $d0, implicit-def $s0, implicit-def $h0, implicit-def $b0, implicit-def $b0_hi, implicit-def $h0_hi, implicit-def $s0_hi, implicit-def $d0_hi, implicit-def $q0_hi, implicit $p0, implicit $z0 {
; CHECK-NEXT: $z0 = MOVPRFX_ZPzZ_S $p0, $z0
; CHECK-NEXT: $z0 = LSL_ZPmI_S renamable $p0, internal $z0, 0
; CHECK-NEXT: $z0 = FSUBR_ZPmZ_S renamable $p0, internal killed $z0, internal killed renamable $z0
diff --git a/llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp b/llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
new file mode 100644
index 00000000000000..6ee64475f0225f
--- /dev/null
+++ b/llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
@@ -0,0 +1,148 @@
+#include "AArch64InstrInfo.h"
+#include "AArch64Subtarget.h"
+#include "AArch64TargetMachine.h"
+#include "AArch64RegisterInfo.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/TargetSelect.h"
+#include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetOptions.h"
+
+#include "gtest/gtest.h"
+
+#define GET_COMPUTE_FEATURES
+#include "AArch64GenInstrInfo.inc"
+
+using namespace llvm;
+
+namespace {
+
+std::unique_ptr<LLVMTargetMachine> createTargetMachine(const std::string &CPU) {
+ auto TT(Triple::normalize("aarch64--"));
+
+ LLVMInitializeAArch64TargetInfo();
+ LLVMInitializeAArch64Target();
+ LLVMInitializeAArch64TargetMC();
+
+ std::string Error;
+ const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error);
+
+ return std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>(
+ TheTarget->createTargetMachine(TT, CPU, "", TargetOptions(), std::nullopt,
+ std::nullopt, CodeGenOptLevel::Default)));
+}
+
+std::unique_ptr<AArch64InstrInfo> createInstrInfo(TargetMachine *TM) {
+ AArch64Subtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
+ std::string(TM->getTargetCPU()),
+ std::string(TM->getTargetFeatureString()), *TM, true);
+ return std::make_unique<AArch64InstrInfo>(ST);
+}
+
+TEST(AArch64LaneBitmasks, SubRegs) {
+ std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine("");
+ ASSERT_TRUE(TM);
+
+ std::unique_ptr<AArch64InstrInfo> II = createInstrInfo(TM.get());
+ ASSERT_TRUE(II);
+
+ const AArch64RegisterInfo &TRI = II->getRegisterInfo();
+
+ // Test that the lane masks for the subregisters 'bsub, hsub, ssub, etc'
+ // are composed correctly.
+ ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::bsub) |
+ TRI.getSubRegIndexLaneMask(AArch64::bsub_hi),
+ TRI.getSubRegIndexLaneMask(AArch64::hsub));
+
+ ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::hsub) |
+ TRI.getSubRegIndexLaneMask(AArch64::hsub_hi),
+ TRI.getSubRegIndexLaneMask(AArch64::ssub));
+
+ ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::ssub) |
+ TRI.getSubRegIndexLaneMask(AArch64::ssub_hi),
+ TRI.getSubRegIndexLaneMask(AArch64::dsub));
+
+ ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub) |
+ TRI.getSubRegIndexLaneMask(AArch64::dsub_hi),
+ TRI.getSubRegIndexLaneMask(AArch64::zsub));
+
+ ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::zsub) |
+ TRI.getSubRegIndexLaneMask(AArch64::zsub_hi),
+ TRI.getSubRegIndexLaneMask(AArch64::zsub0));
+
+ // Test that the lane masks for tuples are composed correctly.
+ ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_bsub) |
+ TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_bsub_hi),
+ TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_hsub));
+
+ ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_hsub) |
+ TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_hsub_hi),
+ TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_ssub));
+
+ ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_ssub) |
+ TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_ssub_hi),
+ TRI.getSubRegIndexLaneMask(AArch64::dsub1));
+
+ ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1) |
+ TRI.getSubRegIndexLaneMask(AArch64::qsub1_then_dsub_hi),
+ TRI.getSubRegIndexLaneMask(AArch64::qsub1));
+
+ ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::sub_32) |
+ TRI.getSubRegIndexLaneMask(AArch64::sub_32_hi),
+ TRI.getSubRegIndexLaneMask(AArch64::sube64));
+
+ ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::subo64_then_sub_32) |
+ TRI.getSubRegIndexLaneMask(AArch64::subo64_then_sub_32_hi),
+ TRI.getSubRegIndexLaneMask(AArch64::subo64));
+
+ // Test that there is no overlap between different (sub)registers
+ // in a tuple.
+ ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub0) &
+ TRI.getSubRegIndexLaneMask(AArch64::dsub1) &
+ TRI.getSubRegIndexLaneMask(AArch64::dsub2) &
+ TRI.getSubRegIndexLaneMask(AArch64::dsub3),
+ LaneBitmask::getNone());
+
+ ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::qsub0) &
+ TRI.getSubRegIndexLaneMask(AArch64::qsub1) &
+ TRI.getSubRegIndexLaneMask(AArch64::qsub2) &
+ TRI.getSubRegIndexLaneMask(AArch64::qsub3),
+ LaneBitmask::getNone());
+
+ ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::zsub0) &
+ TRI.getSubRegIndexLaneMask(AArch64::zsub1) &
+ TRI.getSubRegIndexLaneMask(AArch64::zsub2) &
+ TRI.getSubRegIndexLaneMask(AArch64::zsub3),
+ LaneBitmask::getNone());
+
+ ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::sube32) &
+ TRI.getSubRegIndexLaneMask(AArch64::subo32),
+ LaneBitmask::getNone());
+
+ ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::sube64) &
+ TRI.getSubRegIndexLaneMask(AArch64::subo64),
+ LaneBitmask::getNone());
+
+ // Test that getting a subregister results in the expected subregister.
+ ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::bsub), AArch64::B0);
+ ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::hsub), AArch64::H0);
+ ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::ssub), AArch64::S0);
+ ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub), AArch64::D0);
+ ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::zsub), AArch64::Q0);
+ ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::zsub0), AArch64::Z0);
+
+ ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_bsub), AArch64::B8);
+ ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_hsub), AArch64::H8);
+ ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_ssub), AArch64::S8);
+ ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1), AArch64::D8);
+ ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::qsub1), AArch64::Q8);
+ ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::zsub1), AArch64::Z8);
+
+ ASSERT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::sube64), AArch64::X0);
+ ASSERT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::subo64), AArch64::X1);
+ ASSERT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::sub_32), AArch64::W0);
+ ASSERT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::subo64_then_sub_32), AArch64::W1);
+}
+
+} // namespace
diff --git a/llvm/unittests/Target/AArch64/CMakeLists.txt b/llvm/unittests/Target/AArch64/CMakeLists.txt
index f53668373efee9..449888838acdc6 100644
--- a/llvm/unittests/Target/AArch64/CMakeLists.txt
+++ b/llvm/unittests/Target/AArch64/CMakeLists.txt
@@ -28,6 +28,7 @@ add_llvm_target_unittest(AArch64Tests
InstSizes.cpp
MatrixRegisterAliasing.cpp
SMEAttributesTest.cpp
+ AArch64RegisterInfoTest.cpp
AArch64SVESchedPseudoTest.cpp
Immediates.cpp
)
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index be2a2b3884c73b..4a35fdc7925568 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -1841,6 +1841,7 @@ void RegisterInfoEmitter::debugDump(raw_ostream &OS) {
OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n';
OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n';
OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n';
+ OS << "\tArtificial: " << RC.Artificial << '\n';
OS << "\tAllocatable: " << RC.Allocatable << '\n';
OS << "\tAllocationPriority: " << unsigned(RC.AllocationPriority) << '\n';
OS << "\tBaseClassOrder: " << RC.getBaseClassOrder() << '\n';
>From 8dbcb52e341c3388e4ec9f9a0307601c269935a4 Mon Sep 17 00:00:00 2001
From: Sander de Smalen <sander.desmalen at arm.com>
Date: Wed, 30 Oct 2024 17:22:21 +0000
Subject: [PATCH 2/7] Fixups
---
.../Target/AArch64/AArch64RegisterInfo.cpp | 5 +-
.../AArch64/AArch64RegisterInfoTest.cpp | 118 +++++++++---------
llvm/utils/TableGen/RegisterInfoEmitter.cpp | 1 -
3 files changed, 63 insertions(+), 61 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index 1ef75c6e02e8c7..46cd6f0a95cfa1 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -424,7 +424,7 @@ AArch64RegisterInfo::explainReservedReg(const MachineFunction &MF,
return {};
}
-static SmallVector<MCPhysReg> ReservedHi = {
+static MCPhysReg ReservedHi[] = {
AArch64::B0_HI, AArch64::B1_HI, AArch64::B2_HI, AArch64::B3_HI,
AArch64::B4_HI, AArch64::B5_HI, AArch64::B6_HI, AArch64::B7_HI,
AArch64::B8_HI, AArch64::B9_HI, AArch64::B10_HI, AArch64::B11_HI,
@@ -473,8 +473,7 @@ static SmallVector<MCPhysReg> ReservedHi = {
AArch64::W20_HI, AArch64::W21_HI, AArch64::W22_HI, AArch64::W23_HI,
AArch64::W24_HI, AArch64::W25_HI, AArch64::W26_HI, AArch64::W27_HI,
AArch64::W28_HI, AArch64::W29_HI, AArch64::W30_HI, AArch64::WSP_HI,
- AArch64::WZR_HI
- };
+ AArch64::WZR_HI};
BitVector
AArch64RegisterInfo::getStrictlyReservedRegs(const MachineFunction &MF) const {
diff --git a/llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp b/llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
index 6ee64475f0225f..aff32d6f7a30bb 100644
--- a/llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
+++ b/llvm/unittests/Target/AArch64/AArch64RegisterInfoTest.cpp
@@ -1,7 +1,7 @@
+#include "AArch64RegisterInfo.h"
#include "AArch64InstrInfo.h"
#include "AArch64Subtarget.h"
#include "AArch64TargetMachine.h"
-#include "AArch64RegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
@@ -51,98 +51,102 @@ TEST(AArch64LaneBitmasks, SubRegs) {
// Test that the lane masks for the subregisters 'bsub, hsub, ssub, etc'
// are composed correctly.
- ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::bsub) |
- TRI.getSubRegIndexLaneMask(AArch64::bsub_hi),
+ EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::bsub) |
+ TRI.getSubRegIndexLaneMask(AArch64::bsub_hi),
TRI.getSubRegIndexLaneMask(AArch64::hsub));
- ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::hsub) |
- TRI.getSubRegIndexLaneMask(AArch64::hsub_hi),
+ EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::hsub) |
+ TRI.getSubRegIndexLaneMask(AArch64::hsub_hi),
TRI.getSubRegIndexLaneMask(AArch64::ssub));
- ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::ssub) |
- TRI.getSubRegIndexLaneMask(AArch64::ssub_hi),
+ EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::ssub) |
+ TRI.getSubRegIndexLaneMask(AArch64::ssub_hi),
TRI.getSubRegIndexLaneMask(AArch64::dsub));
- ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub) |
- TRI.getSubRegIndexLaneMask(AArch64::dsub_hi),
+ EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub) |
+ TRI.getSubRegIndexLaneMask(AArch64::dsub_hi),
TRI.getSubRegIndexLaneMask(AArch64::zsub));
- ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::zsub) |
- TRI.getSubRegIndexLaneMask(AArch64::zsub_hi),
+ EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::zsub) |
+ TRI.getSubRegIndexLaneMask(AArch64::zsub_hi),
TRI.getSubRegIndexLaneMask(AArch64::zsub0));
// Test that the lane masks for tuples are composed correctly.
- ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_bsub) |
- TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_bsub_hi),
+ EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_bsub) |
+ TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_bsub_hi),
TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_hsub));
- ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_hsub) |
- TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_hsub_hi),
+ EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_hsub) |
+ TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_hsub_hi),
TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_ssub));
- ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_ssub) |
- TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_ssub_hi),
+ EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_ssub) |
+ TRI.getSubRegIndexLaneMask(AArch64::dsub1_then_ssub_hi),
TRI.getSubRegIndexLaneMask(AArch64::dsub1));
- ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1) |
- TRI.getSubRegIndexLaneMask(AArch64::qsub1_then_dsub_hi),
+ EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub1) |
+ TRI.getSubRegIndexLaneMask(AArch64::qsub1_then_dsub_hi),
TRI.getSubRegIndexLaneMask(AArch64::qsub1));
- ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::sub_32) |
- TRI.getSubRegIndexLaneMask(AArch64::sub_32_hi),
+ EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::sub_32) |
+ TRI.getSubRegIndexLaneMask(AArch64::sub_32_hi),
TRI.getSubRegIndexLaneMask(AArch64::sube64));
- ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::subo64_then_sub_32) |
- TRI.getSubRegIndexLaneMask(AArch64::subo64_then_sub_32_hi),
+ EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::subo64_then_sub_32) |
+ TRI.getSubRegIndexLaneMask(AArch64::subo64_then_sub_32_hi),
TRI.getSubRegIndexLaneMask(AArch64::subo64));
// Test that there is no overlap between different (sub)registers
// in a tuple.
- ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub0) &
- TRI.getSubRegIndexLaneMask(AArch64::dsub1) &
- TRI.getSubRegIndexLaneMask(AArch64::dsub2) &
- TRI.getSubRegIndexLaneMask(AArch64::dsub3),
+ EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::dsub0) &
+ TRI.getSubRegIndexLaneMask(AArch64::dsub1) &
+ TRI.getSubRegIndexLaneMask(AArch64::dsub2) &
+ TRI.getSubRegIndexLaneMask(AArch64::dsub3),
LaneBitmask::getNone());
- ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::qsub0) &
- TRI.getSubRegIndexLaneMask(AArch64::qsub1) &
- TRI.getSubRegIndexLaneMask(AArch64::qsub2) &
- TRI.getSubRegIndexLaneMask(AArch64::qsub3),
+ EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::qsub0) &
+ TRI.getSubRegIndexLaneMask(AArch64::qsub1) &
+ TRI.getSubRegIndexLaneMask(AArch64::qsub2) &
+ TRI.getSubRegIndexLaneMask(AArch64::qsub3),
LaneBitmask::getNone());
- ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::zsub0) &
- TRI.getSubRegIndexLaneMask(AArch64::zsub1) &
- TRI.getSubRegIndexLaneMask(AArch64::zsub2) &
- TRI.getSubRegIndexLaneMask(AArch64::zsub3),
+ EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::zsub0) &
+ TRI.getSubRegIndexLaneMask(AArch64::zsub1) &
+ TRI.getSubRegIndexLaneMask(AArch64::zsub2) &
+ TRI.getSubRegIndexLaneMask(AArch64::zsub3),
LaneBitmask::getNone());
- ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::sube32) &
- TRI.getSubRegIndexLaneMask(AArch64::subo32),
+ EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::sube32) &
+ TRI.getSubRegIndexLaneMask(AArch64::subo32),
LaneBitmask::getNone());
- ASSERT_EQ(TRI.getSubRegIndexLaneMask(AArch64::sube64) &
- TRI.getSubRegIndexLaneMask(AArch64::subo64),
+ EXPECT_EQ(TRI.getSubRegIndexLaneMask(AArch64::sube64) &
+ TRI.getSubRegIndexLaneMask(AArch64::subo64),
LaneBitmask::getNone());
// Test that getting a subregister results in the expected subregister.
- ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::bsub), AArch64::B0);
- ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::hsub), AArch64::H0);
- ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::ssub), AArch64::S0);
- ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub), AArch64::D0);
- ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::zsub), AArch64::Q0);
- ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::zsub0), AArch64::Z0);
-
- ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_bsub), AArch64::B8);
- ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_hsub), AArch64::H8);
- ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_ssub), AArch64::S8);
- ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1), AArch64::D8);
- ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::qsub1), AArch64::Q8);
- ASSERT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::zsub1), AArch64::Z8);
-
- ASSERT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::sube64), AArch64::X0);
- ASSERT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::subo64), AArch64::X1);
- ASSERT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::sub_32), AArch64::W0);
- ASSERT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::subo64_then_sub_32), AArch64::W1);
+ EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::bsub), AArch64::B0);
+ EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::hsub), AArch64::H0);
+ EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::ssub), AArch64::S0);
+ EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub), AArch64::D0);
+ EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::zsub), AArch64::Q0);
+ EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::zsub0), AArch64::Z0);
+
+ EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_bsub),
+ AArch64::B8);
+ EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_hsub),
+ AArch64::H8);
+ EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1_then_ssub),
+ AArch64::S8);
+ EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::dsub1), AArch64::D8);
+ EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::qsub1), AArch64::Q8);
+ EXPECT_EQ(TRI.getSubReg(AArch64::Z0_Z8, AArch64::zsub1), AArch64::Z8);
+
+ EXPECT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::sube64), AArch64::X0);
+ EXPECT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::subo64), AArch64::X1);
+ EXPECT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::sub_32), AArch64::W0);
+ EXPECT_EQ(TRI.getSubReg(AArch64::X0_X1, AArch64::subo64_then_sub_32),
+ AArch64::W1);
}
} // namespace
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index 4a35fdc7925568..be2a2b3884c73b 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -1841,7 +1841,6 @@ void RegisterInfoEmitter::debugDump(raw_ostream &OS) {
OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n';
OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n';
OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n';
- OS << "\tArtificial: " << RC.Artificial << '\n';
OS << "\tAllocatable: " << RC.Allocatable << '\n';
OS << "\tAllocationPriority: " << unsigned(RC.AllocationPriority) << '\n';
OS << "\tBaseClassOrder: " << RC.getBaseClassOrder() << '\n';
>From dbcc23da82b42f194616a046e642ca5d0a53b74a Mon Sep 17 00:00:00 2001
From: Sander de Smalen <sander.desmalen at arm.com>
Date: Mon, 4 Nov 2024 11:49:38 +0000
Subject: [PATCH 3/7] Add const to ReservedHi
---
llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index 46cd6f0a95cfa1..a885ce218f6eb2 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -424,7 +424,7 @@ AArch64RegisterInfo::explainReservedReg(const MachineFunction &MF,
return {};
}
-static MCPhysReg ReservedHi[] = {
+static const MCPhysReg ReservedHi[] = {
AArch64::B0_HI, AArch64::B1_HI, AArch64::B2_HI, AArch64::B3_HI,
AArch64::B4_HI, AArch64::B5_HI, AArch64::B6_HI, AArch64::B7_HI,
AArch64::B8_HI, AArch64::B9_HI, AArch64::B10_HI, AArch64::B11_HI,
>From b4635da5974341bdc10604628e42f7b5fb1a9a99 Mon Sep 17 00:00:00 2001
From: Sander de Smalen <sander.desmalen at arm.com>
Date: Tue, 5 Nov 2024 11:16:16 +0000
Subject: [PATCH 4/7] Regenerate llvm-mca tests
---
.../AArch64/Neoverse/V1-clear-upper-regs.s | 245 ++++++++--------
.../AArch64/Neoverse/V2-clear-upper-regs.s | 270 +++++++++---------
2 files changed, 258 insertions(+), 257 deletions(-)
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-clear-upper-regs.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-clear-upper-regs.s
index ab81f9fb04af35..197996d229b61f 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-clear-upper-regs.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-clear-upper-regs.s
@@ -55,12 +55,12 @@ add v0.16b, v0.16b, v0.16b
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 41
+# CHECK-NEXT: Total Cycles: 107
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 15
-# CHECK-NEXT: uOps Per Cycle: 4.88
-# CHECK-NEXT: IPC: 4.88
+# CHECK-NEXT: uOps Per Cycle: 1.87
+# CHECK-NEXT: IPC: 1.87
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -94,24 +94,25 @@ add v0.16b, v0.16b, v0.16b
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8] [9] [10]
-# CHECK-NEXT: - - - - 0.33 0.33 0.34 0.22 0.22 0.28 0.28 - - - -
+# CHECK-NEXT: - - - - 0.33 0.33 0.34 - - 0.50 0.50 - - - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8] [9] [10] Instructions:
# CHECK-NEXT: - - - - 0.33 0.33 0.34 - - - - - - - - ldr w0, [sp]
-# CHECK-NEXT: - - - - - - - 0.22 0.22 0.28 0.28 - - - - add x0, x0, x0
+# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - add x0, x0, x0
# CHECK: Timeline view:
-# CHECK-NEXT: Index 012345678
+# CHECK-NEXT: 0
+# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeER . ldr w0, [sp]
-# CHECK-NEXT: [0,1] D====eER. add x0, x0, x0
-# CHECK-NEXT: [1,0] DeeeeE-R. ldr w0, [sp]
-# CHECK-NEXT: [1,1] D====eER. add x0, x0, x0
-# CHECK-NEXT: [2,0] DeeeeE-R. ldr w0, [sp]
-# CHECK-NEXT: [2,1] D====eER. add x0, x0, x0
-# CHECK-NEXT: [3,0] D=eeeeER. ldr w0, [sp]
-# CHECK-NEXT: [3,1] D=====eER add x0, x0, x0
+# CHECK: [0,0] DeeeeER . ldr w0, [sp]
+# CHECK-NEXT: [0,1] D====eER . add x0, x0, x0
+# CHECK-NEXT: [1,0] DeeeeE-R . ldr w0, [sp]
+# CHECK-NEXT: [1,1] D=====eER . add x0, x0, x0
+# CHECK-NEXT: [2,0] DeeeeE--R . ldr w0, [sp]
+# CHECK-NEXT: [2,1] D======eER. add x0, x0, x0
+# CHECK-NEXT: [3,0] D=eeeeE--R. ldr w0, [sp]
+# CHECK-NEXT: [3,1] D=======eER add x0, x0, x0
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -120,20 +121,20 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 0.5 ldr w0, [sp]
-# CHECK-NEXT: 1. 4 5.3 0.0 0.0 add x0, x0, x0
-# CHECK-NEXT: 4 3.3 0.6 0.3 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr w0, [sp]
+# CHECK-NEXT: 1. 4 6.5 0.0 0.0 add x0, x0, x0
+# CHECK-NEXT: 4 3.9 0.6 0.6 <total>
# CHECK: [1] Code Region - FPR8-bit
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 44
+# CHECK-NEXT: Total Cycles: 209
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 15
-# CHECK-NEXT: uOps Per Cycle: 4.55
-# CHECK-NEXT: IPC: 4.55
+# CHECK-NEXT: uOps Per Cycle: 0.96
+# CHECK-NEXT: IPC: 0.96
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -175,17 +176,17 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: - - - - - - - - - - - 0.25 0.25 0.25 0.25 fadd d0, d0, d0
# CHECK: Timeline view:
-# CHECK-NEXT: 01
+# CHECK-NEXT: 0123456
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER .. ldr b0, [sp]
-# CHECK-NEXT: [0,1] D======eeER. fadd d0, d0, d0
-# CHECK-NEXT: [1,0] DeeeeeeE--R. ldr b0, [sp]
-# CHECK-NEXT: [1,1] D======eeER. fadd d0, d0, d0
-# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr b0, [sp]
-# CHECK-NEXT: [2,1] D======eeER. fadd d0, d0, d0
-# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr b0, [sp]
-# CHECK-NEXT: [3,1] D=======eeER fadd d0, d0, d0
+# CHECK: [0,0] DeeeeeeER . .. ldr b0, [sp]
+# CHECK-NEXT: [0,1] D======eeER .. fadd d0, d0, d0
+# CHECK-NEXT: [1,0] DeeeeeeE--R .. ldr b0, [sp]
+# CHECK-NEXT: [1,1] D========eeER .. fadd d0, d0, d0
+# CHECK-NEXT: [2,0] DeeeeeeE----R .. ldr b0, [sp]
+# CHECK-NEXT: [2,1] D==========eeER.. fadd d0, d0, d0
+# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ldr b0, [sp]
+# CHECK-NEXT: [3,1] D============eeER fadd d0, d0, d0
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -194,20 +195,20 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr b0, [sp]
-# CHECK-NEXT: 1. 4 7.3 0.0 0.0 fadd d0, d0, d0
-# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ldr b0, [sp]
+# CHECK-NEXT: 1. 4 10.0 0.0 0.0 fadd d0, d0, d0
+# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
# CHECK: [2] Code Region - FPR16-bit
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 44
+# CHECK-NEXT: Total Cycles: 209
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 15
-# CHECK-NEXT: uOps Per Cycle: 4.55
-# CHECK-NEXT: IPC: 4.55
+# CHECK-NEXT: uOps Per Cycle: 0.96
+# CHECK-NEXT: IPC: 0.96
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -249,17 +250,17 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: - - - - - - - - - - - 0.25 0.25 0.25 0.25 fadd d0, d0, d0
# CHECK: Timeline view:
-# CHECK-NEXT: 01
+# CHECK-NEXT: 0123456
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER .. ldr h0, [sp]
-# CHECK-NEXT: [0,1] D======eeER. fadd d0, d0, d0
-# CHECK-NEXT: [1,0] DeeeeeeE--R. ldr h0, [sp]
-# CHECK-NEXT: [1,1] D======eeER. fadd d0, d0, d0
-# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr h0, [sp]
-# CHECK-NEXT: [2,1] D======eeER. fadd d0, d0, d0
-# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr h0, [sp]
-# CHECK-NEXT: [3,1] D=======eeER fadd d0, d0, d0
+# CHECK: [0,0] DeeeeeeER . .. ldr h0, [sp]
+# CHECK-NEXT: [0,1] D======eeER .. fadd d0, d0, d0
+# CHECK-NEXT: [1,0] DeeeeeeE--R .. ldr h0, [sp]
+# CHECK-NEXT: [1,1] D========eeER .. fadd d0, d0, d0
+# CHECK-NEXT: [2,0] DeeeeeeE----R .. ldr h0, [sp]
+# CHECK-NEXT: [2,1] D==========eeER.. fadd d0, d0, d0
+# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ldr h0, [sp]
+# CHECK-NEXT: [3,1] D============eeER fadd d0, d0, d0
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -268,20 +269,20 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr h0, [sp]
-# CHECK-NEXT: 1. 4 7.3 0.0 0.0 fadd d0, d0, d0
-# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ldr h0, [sp]
+# CHECK-NEXT: 1. 4 10.0 0.0 0.0 fadd d0, d0, d0
+# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
# CHECK: [3] Code Region - FPR32-bit
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 44
+# CHECK-NEXT: Total Cycles: 209
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 15
-# CHECK-NEXT: uOps Per Cycle: 4.55
-# CHECK-NEXT: IPC: 4.55
+# CHECK-NEXT: uOps Per Cycle: 0.96
+# CHECK-NEXT: IPC: 0.96
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -323,17 +324,17 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: - - - - - - - - - - - 0.25 0.25 0.25 0.25 fadd d0, d0, d0
# CHECK: Timeline view:
-# CHECK-NEXT: 01
+# CHECK-NEXT: 0123456
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER .. ldr s0, [sp]
-# CHECK-NEXT: [0,1] D======eeER. fadd d0, d0, d0
-# CHECK-NEXT: [1,0] DeeeeeeE--R. ldr s0, [sp]
-# CHECK-NEXT: [1,1] D======eeER. fadd d0, d0, d0
-# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr s0, [sp]
-# CHECK-NEXT: [2,1] D======eeER. fadd d0, d0, d0
-# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr s0, [sp]
-# CHECK-NEXT: [3,1] D=======eeER fadd d0, d0, d0
+# CHECK: [0,0] DeeeeeeER . .. ldr s0, [sp]
+# CHECK-NEXT: [0,1] D======eeER .. fadd d0, d0, d0
+# CHECK-NEXT: [1,0] DeeeeeeE--R .. ldr s0, [sp]
+# CHECK-NEXT: [1,1] D========eeER .. fadd d0, d0, d0
+# CHECK-NEXT: [2,0] DeeeeeeE----R .. ldr s0, [sp]
+# CHECK-NEXT: [2,1] D==========eeER.. fadd d0, d0, d0
+# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ldr s0, [sp]
+# CHECK-NEXT: [3,1] D============eeER fadd d0, d0, d0
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -342,20 +343,20 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr s0, [sp]
-# CHECK-NEXT: 1. 4 7.3 0.0 0.0 fadd d0, d0, d0
-# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ldr s0, [sp]
+# CHECK-NEXT: 1. 4 10.0 0.0 0.0 fadd d0, d0, d0
+# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
# CHECK: [4] Code Region - SIMD64-bit-b
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 44
+# CHECK-NEXT: Total Cycles: 209
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 15
-# CHECK-NEXT: uOps Per Cycle: 4.55
-# CHECK-NEXT: IPC: 4.55
+# CHECK-NEXT: uOps Per Cycle: 0.96
+# CHECK-NEXT: IPC: 0.96
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -397,17 +398,17 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: - - - - - - - - - - - 0.25 0.25 0.25 0.25 add v0.16b, v0.16b, v0.16b
# CHECK: Timeline view:
-# CHECK-NEXT: 01
+# CHECK-NEXT: 0123456
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER .. ld1 { v0.8b }, [sp]
-# CHECK-NEXT: [0,1] D======eeER. add v0.16b, v0.16b, v0.16b
-# CHECK-NEXT: [1,0] DeeeeeeE--R. ld1 { v0.8b }, [sp]
-# CHECK-NEXT: [1,1] D======eeER. add v0.16b, v0.16b, v0.16b
-# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.8b }, [sp]
-# CHECK-NEXT: [2,1] D======eeER. add v0.16b, v0.16b, v0.16b
-# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.8b }, [sp]
-# CHECK-NEXT: [3,1] D=======eeER add v0.16b, v0.16b, v0.16b
+# CHECK: [0,0] DeeeeeeER . .. ld1 { v0.8b }, [sp]
+# CHECK-NEXT: [0,1] D======eeER .. add v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: [1,0] DeeeeeeE--R .. ld1 { v0.8b }, [sp]
+# CHECK-NEXT: [1,1] D========eeER .. add v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: [2,0] DeeeeeeE----R .. ld1 { v0.8b }, [sp]
+# CHECK-NEXT: [2,1] D==========eeER.. add v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ld1 { v0.8b }, [sp]
+# CHECK-NEXT: [3,1] D============eeER add v0.16b, v0.16b, v0.16b
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -416,20 +417,20 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.8b }, [sp]
-# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add v0.16b, v0.16b, v0.16b
-# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ld1 { v0.8b }, [sp]
+# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
# CHECK: [5] Code Region - SIMD64-bit-h
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 44
+# CHECK-NEXT: Total Cycles: 209
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 15
-# CHECK-NEXT: uOps Per Cycle: 4.55
-# CHECK-NEXT: IPC: 4.55
+# CHECK-NEXT: uOps Per Cycle: 0.96
+# CHECK-NEXT: IPC: 0.96
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -471,17 +472,17 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: - - - - - - - - - - - 0.25 0.25 0.25 0.25 add v0.8h, v0.8h, v0.8h
# CHECK: Timeline view:
-# CHECK-NEXT: 01
+# CHECK-NEXT: 0123456
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER .. ld1 { v0.4h }, [sp]
-# CHECK-NEXT: [0,1] D======eeER. add v0.8h, v0.8h, v0.8h
-# CHECK-NEXT: [1,0] DeeeeeeE--R. ld1 { v0.4h }, [sp]
-# CHECK-NEXT: [1,1] D======eeER. add v0.8h, v0.8h, v0.8h
-# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.4h }, [sp]
-# CHECK-NEXT: [2,1] D======eeER. add v0.8h, v0.8h, v0.8h
-# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.4h }, [sp]
-# CHECK-NEXT: [3,1] D=======eeER add v0.8h, v0.8h, v0.8h
+# CHECK: [0,0] DeeeeeeER . .. ld1 { v0.4h }, [sp]
+# CHECK-NEXT: [0,1] D======eeER .. add v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: [1,0] DeeeeeeE--R .. ld1 { v0.4h }, [sp]
+# CHECK-NEXT: [1,1] D========eeER .. add v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: [2,0] DeeeeeeE----R .. ld1 { v0.4h }, [sp]
+# CHECK-NEXT: [2,1] D==========eeER.. add v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ld1 { v0.4h }, [sp]
+# CHECK-NEXT: [3,1] D============eeER add v0.8h, v0.8h, v0.8h
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -490,20 +491,20 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.4h }, [sp]
-# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add v0.8h, v0.8h, v0.8h
-# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ld1 { v0.4h }, [sp]
+# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
# CHECK: [6] Code Region - SIMD64-bit-s
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 44
+# CHECK-NEXT: Total Cycles: 209
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 15
-# CHECK-NEXT: uOps Per Cycle: 4.55
-# CHECK-NEXT: IPC: 4.55
+# CHECK-NEXT: uOps Per Cycle: 0.96
+# CHECK-NEXT: IPC: 0.96
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -545,17 +546,17 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: - - - - - - - - - - - 0.25 0.25 0.25 0.25 add v0.4s, v0.4s, v0.4s
# CHECK: Timeline view:
-# CHECK-NEXT: 01
+# CHECK-NEXT: 0123456
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER .. ld1 { v0.2s }, [sp]
-# CHECK-NEXT: [0,1] D======eeER. add v0.4s, v0.4s, v0.4s
-# CHECK-NEXT: [1,0] DeeeeeeE--R. ld1 { v0.2s }, [sp]
-# CHECK-NEXT: [1,1] D======eeER. add v0.4s, v0.4s, v0.4s
-# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.2s }, [sp]
-# CHECK-NEXT: [2,1] D======eeER. add v0.4s, v0.4s, v0.4s
-# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.2s }, [sp]
-# CHECK-NEXT: [3,1] D=======eeER add v0.4s, v0.4s, v0.4s
+# CHECK: [0,0] DeeeeeeER . .. ld1 { v0.2s }, [sp]
+# CHECK-NEXT: [0,1] D======eeER .. add v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: [1,0] DeeeeeeE--R .. ld1 { v0.2s }, [sp]
+# CHECK-NEXT: [1,1] D========eeER .. add v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: [2,0] DeeeeeeE----R .. ld1 { v0.2s }, [sp]
+# CHECK-NEXT: [2,1] D==========eeER.. add v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ld1 { v0.2s }, [sp]
+# CHECK-NEXT: [3,1] D============eeER add v0.4s, v0.4s, v0.4s
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -564,20 +565,20 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.2s }, [sp]
-# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add v0.4s, v0.4s, v0.4s
-# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ld1 { v0.2s }, [sp]
+# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
# CHECK: [7] Code Region - SIMD64-bit-d
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 44
+# CHECK-NEXT: Total Cycles: 209
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 15
-# CHECK-NEXT: uOps Per Cycle: 4.55
-# CHECK-NEXT: IPC: 4.55
+# CHECK-NEXT: uOps Per Cycle: 0.96
+# CHECK-NEXT: IPC: 0.96
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -619,17 +620,17 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: - - - - - - - - - - - 0.25 0.25 0.25 0.25 add v0.2d, v0.2d, v0.2d
# CHECK: Timeline view:
-# CHECK-NEXT: 01
+# CHECK-NEXT: 0123456
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER .. ld1 { v0.1d }, [sp]
-# CHECK-NEXT: [0,1] D======eeER. add v0.2d, v0.2d, v0.2d
-# CHECK-NEXT: [1,0] DeeeeeeE--R. ld1 { v0.1d }, [sp]
-# CHECK-NEXT: [1,1] D======eeER. add v0.2d, v0.2d, v0.2d
-# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.1d }, [sp]
-# CHECK-NEXT: [2,1] D======eeER. add v0.2d, v0.2d, v0.2d
-# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.1d }, [sp]
-# CHECK-NEXT: [3,1] D=======eeER add v0.2d, v0.2d, v0.2d
+# CHECK: [0,0] DeeeeeeER . .. ld1 { v0.1d }, [sp]
+# CHECK-NEXT: [0,1] D======eeER .. add v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: [1,0] DeeeeeeE--R .. ld1 { v0.1d }, [sp]
+# CHECK-NEXT: [1,1] D========eeER .. add v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: [2,0] DeeeeeeE----R .. ld1 { v0.1d }, [sp]
+# CHECK-NEXT: [2,1] D==========eeER.. add v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ld1 { v0.1d }, [sp]
+# CHECK-NEXT: [3,1] D============eeER add v0.2d, v0.2d, v0.2d
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -638,9 +639,9 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.1d }, [sp]
-# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add v0.2d, v0.2d, v0.2d
-# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ld1 { v0.1d }, [sp]
+# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
# CHECK: [8] Code Region - ins
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-clear-upper-regs.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-clear-upper-regs.s
index fd2083dc1277a0..c15ed9230edc90 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-clear-upper-regs.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-clear-upper-regs.s
@@ -55,12 +55,12 @@ add z0.s, z0.s, z0.s
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 44
+# CHECK-NEXT: Total Cycles: 209
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 16
-# CHECK-NEXT: uOps Per Cycle: 4.55
-# CHECK-NEXT: IPC: 4.55
+# CHECK-NEXT: uOps Per Cycle: 0.96
+# CHECK-NEXT: IPC: 0.96
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -104,17 +104,17 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add z0.d, z0.d, z0.d
# CHECK: Timeline view:
-# CHECK-NEXT: 01
+# CHECK-NEXT: 0123456
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER .. ldr b0, [sp]
-# CHECK-NEXT: [0,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [1,0] DeeeeeeE--R. ldr b0, [sp]
-# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr b0, [sp]
-# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr b0, [sp]
-# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
+# CHECK: [0,0] DeeeeeeER . .. ldr b0, [sp]
+# CHECK-NEXT: [0,1] D======eeER .. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,0] DeeeeeeE--R .. ldr b0, [sp]
+# CHECK-NEXT: [1,1] D========eeER .. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [2,0] DeeeeeeE----R .. ldr b0, [sp]
+# CHECK-NEXT: [2,1] D==========eeER.. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ldr b0, [sp]
+# CHECK-NEXT: [3,1] D============eeER add z0.d, z0.d, z0.d
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -123,20 +123,20 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr b0, [sp]
-# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
-# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ldr b0, [sp]
+# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add z0.d, z0.d, z0.d
+# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
# CHECK: [1] Code Region - FPR16-bit
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 44
+# CHECK-NEXT: Total Cycles: 209
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 16
-# CHECK-NEXT: uOps Per Cycle: 4.55
-# CHECK-NEXT: IPC: 4.55
+# CHECK-NEXT: uOps Per Cycle: 0.96
+# CHECK-NEXT: IPC: 0.96
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -180,17 +180,17 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add z0.d, z0.d, z0.d
# CHECK: Timeline view:
-# CHECK-NEXT: 01
+# CHECK-NEXT: 0123456
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER .. ldr h0, [sp]
-# CHECK-NEXT: [0,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [1,0] DeeeeeeE--R. ldr h0, [sp]
-# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr h0, [sp]
-# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr h0, [sp]
-# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
+# CHECK: [0,0] DeeeeeeER . .. ldr h0, [sp]
+# CHECK-NEXT: [0,1] D======eeER .. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,0] DeeeeeeE--R .. ldr h0, [sp]
+# CHECK-NEXT: [1,1] D========eeER .. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [2,0] DeeeeeeE----R .. ldr h0, [sp]
+# CHECK-NEXT: [2,1] D==========eeER.. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ldr h0, [sp]
+# CHECK-NEXT: [3,1] D============eeER add z0.d, z0.d, z0.d
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -199,20 +199,20 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr h0, [sp]
-# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
-# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ldr h0, [sp]
+# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add z0.d, z0.d, z0.d
+# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
# CHECK: [2] Code Region - FPR32-bit
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 44
+# CHECK-NEXT: Total Cycles: 209
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 16
-# CHECK-NEXT: uOps Per Cycle: 4.55
-# CHECK-NEXT: IPC: 4.55
+# CHECK-NEXT: uOps Per Cycle: 0.96
+# CHECK-NEXT: IPC: 0.96
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -256,17 +256,17 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add z0.d, z0.d, z0.d
# CHECK: Timeline view:
-# CHECK-NEXT: 01
+# CHECK-NEXT: 0123456
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER .. ldr s0, [sp]
-# CHECK-NEXT: [0,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [1,0] DeeeeeeE--R. ldr s0, [sp]
-# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr s0, [sp]
-# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr s0, [sp]
-# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
+# CHECK: [0,0] DeeeeeeER . .. ldr s0, [sp]
+# CHECK-NEXT: [0,1] D======eeER .. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,0] DeeeeeeE--R .. ldr s0, [sp]
+# CHECK-NEXT: [1,1] D========eeER .. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [2,0] DeeeeeeE----R .. ldr s0, [sp]
+# CHECK-NEXT: [2,1] D==========eeER.. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ldr s0, [sp]
+# CHECK-NEXT: [3,1] D============eeER add z0.d, z0.d, z0.d
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -275,20 +275,20 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr s0, [sp]
-# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
-# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ldr s0, [sp]
+# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add z0.d, z0.d, z0.d
+# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
# CHECK: [3] Code Region - FPR64-bit
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 44
+# CHECK-NEXT: Total Cycles: 209
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 16
-# CHECK-NEXT: uOps Per Cycle: 4.55
-# CHECK-NEXT: IPC: 4.55
+# CHECK-NEXT: uOps Per Cycle: 0.96
+# CHECK-NEXT: IPC: 0.96
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -332,17 +332,17 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add z0.d, z0.d, z0.d
# CHECK: Timeline view:
-# CHECK-NEXT: 01
+# CHECK-NEXT: 0123456
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER .. ldr d0, [sp]
-# CHECK-NEXT: [0,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [1,0] DeeeeeeE--R. ldr d0, [sp]
-# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr d0, [sp]
-# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr d0, [sp]
-# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
+# CHECK: [0,0] DeeeeeeER . .. ldr d0, [sp]
+# CHECK-NEXT: [0,1] D======eeER .. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,0] DeeeeeeE--R .. ldr d0, [sp]
+# CHECK-NEXT: [1,1] D========eeER .. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [2,0] DeeeeeeE----R .. ldr d0, [sp]
+# CHECK-NEXT: [2,1] D==========eeER.. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ldr d0, [sp]
+# CHECK-NEXT: [3,1] D============eeER add z0.d, z0.d, z0.d
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -351,20 +351,20 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr d0, [sp]
-# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
-# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ldr d0, [sp]
+# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add z0.d, z0.d, z0.d
+# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
# CHECK: [4] Code Region - FPR128-bit
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 44
+# CHECK-NEXT: Total Cycles: 209
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 16
-# CHECK-NEXT: uOps Per Cycle: 4.55
-# CHECK-NEXT: IPC: 4.55
+# CHECK-NEXT: uOps Per Cycle: 0.96
+# CHECK-NEXT: IPC: 0.96
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -408,17 +408,17 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add z0.d, z0.d, z0.d
# CHECK: Timeline view:
-# CHECK-NEXT: 01
+# CHECK-NEXT: 0123456
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER .. ldr q0, [sp]
-# CHECK-NEXT: [0,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [1,0] DeeeeeeE--R. ldr q0, [sp]
-# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr q0, [sp]
-# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr q0, [sp]
-# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
+# CHECK: [0,0] DeeeeeeER . .. ldr q0, [sp]
+# CHECK-NEXT: [0,1] D======eeER .. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,0] DeeeeeeE--R .. ldr q0, [sp]
+# CHECK-NEXT: [1,1] D========eeER .. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [2,0] DeeeeeeE----R .. ldr q0, [sp]
+# CHECK-NEXT: [2,1] D==========eeER.. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ldr q0, [sp]
+# CHECK-NEXT: [3,1] D============eeER add z0.d, z0.d, z0.d
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -427,20 +427,20 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr q0, [sp]
-# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
-# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ldr q0, [sp]
+# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add z0.d, z0.d, z0.d
+# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
# CHECK: [5] Code Region - SIMD64-bit-b
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 44
+# CHECK-NEXT: Total Cycles: 209
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 16
-# CHECK-NEXT: uOps Per Cycle: 4.55
-# CHECK-NEXT: IPC: 4.55
+# CHECK-NEXT: uOps Per Cycle: 0.96
+# CHECK-NEXT: IPC: 0.96
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -484,17 +484,17 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add z0.d, z0.d, z0.d
# CHECK: Timeline view:
-# CHECK-NEXT: 01
+# CHECK-NEXT: 0123456
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER .. ld1 { v0.8b }, [sp]
-# CHECK-NEXT: [0,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [1,0] DeeeeeeE--R. ld1 { v0.8b }, [sp]
-# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.8b }, [sp]
-# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.8b }, [sp]
-# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
+# CHECK: [0,0] DeeeeeeER . .. ld1 { v0.8b }, [sp]
+# CHECK-NEXT: [0,1] D======eeER .. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,0] DeeeeeeE--R .. ld1 { v0.8b }, [sp]
+# CHECK-NEXT: [1,1] D========eeER .. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [2,0] DeeeeeeE----R .. ld1 { v0.8b }, [sp]
+# CHECK-NEXT: [2,1] D==========eeER.. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ld1 { v0.8b }, [sp]
+# CHECK-NEXT: [3,1] D============eeER add z0.d, z0.d, z0.d
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -503,20 +503,20 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.8b }, [sp]
-# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
-# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ld1 { v0.8b }, [sp]
+# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add z0.d, z0.d, z0.d
+# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
# CHECK: [6] Code Region - SIMD64-bit-h
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 44
+# CHECK-NEXT: Total Cycles: 209
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 16
-# CHECK-NEXT: uOps Per Cycle: 4.55
-# CHECK-NEXT: IPC: 4.55
+# CHECK-NEXT: uOps Per Cycle: 0.96
+# CHECK-NEXT: IPC: 0.96
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -560,17 +560,17 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add z0.d, z0.d, z0.d
# CHECK: Timeline view:
-# CHECK-NEXT: 01
+# CHECK-NEXT: 0123456
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER .. ld1 { v0.4h }, [sp]
-# CHECK-NEXT: [0,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [1,0] DeeeeeeE--R. ld1 { v0.4h }, [sp]
-# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.4h }, [sp]
-# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.4h }, [sp]
-# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
+# CHECK: [0,0] DeeeeeeER . .. ld1 { v0.4h }, [sp]
+# CHECK-NEXT: [0,1] D======eeER .. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,0] DeeeeeeE--R .. ld1 { v0.4h }, [sp]
+# CHECK-NEXT: [1,1] D========eeER .. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [2,0] DeeeeeeE----R .. ld1 { v0.4h }, [sp]
+# CHECK-NEXT: [2,1] D==========eeER.. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ld1 { v0.4h }, [sp]
+# CHECK-NEXT: [3,1] D============eeER add z0.d, z0.d, z0.d
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -579,20 +579,20 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.4h }, [sp]
-# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
-# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ld1 { v0.4h }, [sp]
+# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add z0.d, z0.d, z0.d
+# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
# CHECK: [7] Code Region - SIMD64-bit-s
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 44
+# CHECK-NEXT: Total Cycles: 209
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 16
-# CHECK-NEXT: uOps Per Cycle: 4.55
-# CHECK-NEXT: IPC: 4.55
+# CHECK-NEXT: uOps Per Cycle: 0.96
+# CHECK-NEXT: IPC: 0.96
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -636,17 +636,17 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add z0.d, z0.d, z0.d
# CHECK: Timeline view:
-# CHECK-NEXT: 01
+# CHECK-NEXT: 0123456
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER .. ld1 { v0.2s }, [sp]
-# CHECK-NEXT: [0,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [1,0] DeeeeeeE--R. ld1 { v0.2s }, [sp]
-# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.2s }, [sp]
-# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.2s }, [sp]
-# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
+# CHECK: [0,0] DeeeeeeER . .. ld1 { v0.2s }, [sp]
+# CHECK-NEXT: [0,1] D======eeER .. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,0] DeeeeeeE--R .. ld1 { v0.2s }, [sp]
+# CHECK-NEXT: [1,1] D========eeER .. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [2,0] DeeeeeeE----R .. ld1 { v0.2s }, [sp]
+# CHECK-NEXT: [2,1] D==========eeER.. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ld1 { v0.2s }, [sp]
+# CHECK-NEXT: [3,1] D============eeER add z0.d, z0.d, z0.d
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -655,20 +655,20 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.2s }, [sp]
-# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
-# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ld1 { v0.2s }, [sp]
+# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add z0.d, z0.d, z0.d
+# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
# CHECK: [8] Code Region - SIMD64-bit-d
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 44
+# CHECK-NEXT: Total Cycles: 209
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 16
-# CHECK-NEXT: uOps Per Cycle: 4.55
-# CHECK-NEXT: IPC: 4.55
+# CHECK-NEXT: uOps Per Cycle: 0.96
+# CHECK-NEXT: IPC: 0.96
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -712,17 +712,17 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add z0.d, z0.d, z0.d
# CHECK: Timeline view:
-# CHECK-NEXT: 01
+# CHECK-NEXT: 0123456
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER .. ld1 { v0.1d }, [sp]
-# CHECK-NEXT: [0,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [1,0] DeeeeeeE--R. ld1 { v0.1d }, [sp]
-# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.1d }, [sp]
-# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.1d }, [sp]
-# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
+# CHECK: [0,0] DeeeeeeER . .. ld1 { v0.1d }, [sp]
+# CHECK-NEXT: [0,1] D======eeER .. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,0] DeeeeeeE--R .. ld1 { v0.1d }, [sp]
+# CHECK-NEXT: [1,1] D========eeER .. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [2,0] DeeeeeeE----R .. ld1 { v0.1d }, [sp]
+# CHECK-NEXT: [2,1] D==========eeER.. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ld1 { v0.1d }, [sp]
+# CHECK-NEXT: [3,1] D============eeER add z0.d, z0.d, z0.d
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -731,9 +731,9 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.1d }, [sp]
-# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
-# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ld1 { v0.1d }, [sp]
+# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add z0.d, z0.d, z0.d
+# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
# CHECK: [9] Code Region - insr
>From c96fbce567808a6f7202eff44a4dc973ebb586a1 Mon Sep 17 00:00:00 2001
From: Sander de Smalen <sander.desmalen at arm.com>
Date: Tue, 5 Nov 2024 11:27:51 +0000
Subject: [PATCH 5/7] Document the _hi SubRegIndexes
---
.../lib/Target/AArch64/AArch64RegisterInfo.td | 24 +++++++++++++------
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
index 5f7f6aa7a7bf99..abf000a6e41919 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -20,8 +20,7 @@ class AArch64Reg<bits<16> enc, string n, list<Register> subregs = [],
let Namespace = "AArch64" in {
// SubRegIndexes for GPR registers
- def sub_32 : SubRegIndex<32, 0>;
- def sub_32_hi: SubRegIndex<32, 32>;
+ def sub_32 : SubRegIndex<32>;
def sube64 : SubRegIndex<64>;
def subo64 : SubRegIndex<64>;
def sube32 : SubRegIndex<32>;
@@ -29,15 +28,26 @@ let Namespace = "AArch64" in {
// SubRegIndexes for FPR/Vector registers
def bsub : SubRegIndex<8, 0>;
- def bsub_hi : SubRegIndex<8, 8>;
def hsub : SubRegIndex<16, 0>;
- def hsub_hi : SubRegIndex<16, 16>;
def ssub : SubRegIndex<32, 0>;
- def ssub_hi : SubRegIndex<32, 32>;
def dsub : SubRegIndex<64, 0>;
- def dsub_hi : SubRegIndex<64, 64>;
def zsub : SubRegIndex<128, 0>;
- def zsub_hi : SubRegIndex<-1, 128>;
+
+ // The _hi SubRegIndexes describe the high bits of a register which are not
+ // separately addressable. They need to be described so that partially
+ // overlapping registers end up with a different lane mask. This is required
+ // to enable subreg liveness tracking.
+ //
+ // For example: 8-bit B0 is a sub-register of 16-bit H0.
+ // * B0 is described with 'bsub'.
+ // * H0 is described with 'bsub + bsub_hi' == 'hsub'.
+ def bsub_hi : SubRegIndex<8, 8>;
+ def hsub_hi : SubRegIndex<16, 16>;
+ def ssub_hi : SubRegIndex<32, 32>;
+ def dsub_hi : SubRegIndex<64, 64>;
+ def zsub_hi : SubRegIndex<-1, 128>;
+ // sub_32_hi describes the top 32 bits in e.g. X0
+ def sub_32_hi : SubRegIndex<32, 32>;
// Note: Code depends on these having consecutive numbers
def zsub0 : SubRegIndex<-1>;
def zsub1 : SubRegIndex<-1>;
>From a82ac4633a81e3e2819c48f05e028e02d59bdb79 Mon Sep 17 00:00:00 2001
From: Sander de Smalen <sander.desmalen at arm.com>
Date: Fri, 8 Nov 2024 12:14:11 +0000
Subject: [PATCH 6/7] Fix llvm-mca not to consider artificial subregs
---
llvm/include/llvm/MC/MCRegisterInfo.h | 6 +
llvm/lib/MCA/HardwareUnits/RegisterFile.cpp | 14 +-
.../AArch64/Neoverse/V1-clear-upper-regs.s | 245 ++++++++--------
.../AArch64/Neoverse/V2-clear-upper-regs.s | 270 +++++++++---------
llvm/utils/TableGen/RegisterInfoEmitter.cpp | 6 +-
5 files changed, 277 insertions(+), 264 deletions(-)
diff --git a/llvm/include/llvm/MC/MCRegisterInfo.h b/llvm/include/llvm/MC/MCRegisterInfo.h
index 6db42878d2e521..0ddda5b53b5f4e 100644
--- a/llvm/include/llvm/MC/MCRegisterInfo.h
+++ b/llvm/include/llvm/MC/MCRegisterInfo.h
@@ -129,6 +129,9 @@ struct MCRegisterDesc {
// Is true for constant registers.
bool IsConstant;
+
+ // Is true for artificial registers.
+ bool IsArtificial;
};
/// MCRegisterInfo base class - We assume that the target defines a static
@@ -396,6 +399,9 @@ class MCRegisterInfo {
/// Returns true if the given register is constant.
bool isConstant(MCRegister RegNo) const { return get(RegNo).IsConstant; }
+ /// Returns true if the given register is artificial.
+ bool isArtificial(MCRegister RegNo) const { return get(RegNo).IsArtificial; }
+
/// Return the number of registers this target has (useful for
/// sizing arrays holding per register information)
unsigned getNumRegs() const {
diff --git a/llvm/lib/MCA/HardwareUnits/RegisterFile.cpp b/llvm/lib/MCA/HardwareUnits/RegisterFile.cpp
index 3c1c35adf88977..cfab40a1c1595b 100644
--- a/llvm/lib/MCA/HardwareUnits/RegisterFile.cpp
+++ b/llvm/lib/MCA/HardwareUnits/RegisterFile.cpp
@@ -24,6 +24,11 @@ namespace mca {
const unsigned WriteRef::INVALID_IID = std::numeric_limits<unsigned>::max();
+static std::function<bool(MCPhysReg)>
+isNonArtificial(const MCRegisterInfo &MRI) {
+ return [&MRI](MCPhysReg R) { return !MRI.isArtificial(R); };
+}
+
WriteRef::WriteRef(unsigned SourceIndex, WriteState *WS)
: IID(SourceIndex), WriteBackCycle(), WriteResID(), RegisterID(),
Write(WS) {}
@@ -282,7 +287,8 @@ void RegisterFile::addRegisterWrite(WriteRef Write,
MCPhysReg ZeroRegisterID =
WS.clearsSuperRegisters() ? RegID : WS.getRegisterID();
ZeroRegisters.setBitVal(ZeroRegisterID, IsWriteZero);
- for (MCPhysReg I : MRI.subregs(ZeroRegisterID))
+ for (MCPhysReg I :
+ make_filter_range(MRI.subregs(ZeroRegisterID), isNonArtificial(MRI)))
ZeroRegisters.setBitVal(I, IsWriteZero);
// If this move has been eliminated, then method tryEliminateMoveOrSwap should
@@ -304,7 +310,8 @@ void RegisterFile::addRegisterWrite(WriteRef Write,
// Update the mapping for register RegID including its sub-registers.
RegisterMappings[RegID].first = Write;
RegisterMappings[RegID].second.AliasRegID = 0U;
- for (MCPhysReg I : MRI.subregs(RegID)) {
+ for (MCPhysReg I :
+ make_filter_range(MRI.subregs(RegID), isNonArtificial(MRI))) {
RegisterMappings[I].first = Write;
RegisterMappings[I].second.AliasRegID = 0U;
}
@@ -472,7 +479,8 @@ bool RegisterFile::tryEliminateMoveOrSwap(MutableArrayRef<WriteState> Writes,
AliasedReg = RMAlias.AliasRegID;
RegisterMappings[AliasReg].second.AliasRegID = AliasedReg;
- for (MCPhysReg I : MRI.subregs(AliasReg))
+ for (MCPhysReg I :
+ make_filter_range(MRI.subregs(AliasReg), isNonArtificial(MRI)))
RegisterMappings[I].second.AliasRegID = AliasedReg;
if (ZeroRegisters[RS.getRegisterID()]) {
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-clear-upper-regs.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-clear-upper-regs.s
index 197996d229b61f..ab81f9fb04af35 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-clear-upper-regs.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-clear-upper-regs.s
@@ -55,12 +55,12 @@ add v0.16b, v0.16b, v0.16b
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 107
+# CHECK-NEXT: Total Cycles: 41
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 15
-# CHECK-NEXT: uOps Per Cycle: 1.87
-# CHECK-NEXT: IPC: 1.87
+# CHECK-NEXT: uOps Per Cycle: 4.88
+# CHECK-NEXT: IPC: 4.88
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -94,25 +94,24 @@ add v0.16b, v0.16b, v0.16b
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8] [9] [10]
-# CHECK-NEXT: - - - - 0.33 0.33 0.34 - - 0.50 0.50 - - - -
+# CHECK-NEXT: - - - - 0.33 0.33 0.34 0.22 0.22 0.28 0.28 - - - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2] [3.0] [3.1] [4] [5] [6.0] [6.1] [7] [8] [9] [10] Instructions:
# CHECK-NEXT: - - - - 0.33 0.33 0.34 - - - - - - - - ldr w0, [sp]
-# CHECK-NEXT: - - - - - - - - - 0.50 0.50 - - - - add x0, x0, x0
+# CHECK-NEXT: - - - - - - - 0.22 0.22 0.28 0.28 - - - - add x0, x0, x0
# CHECK: Timeline view:
-# CHECK-NEXT: 0
-# CHECK-NEXT: Index 0123456789
+# CHECK-NEXT: Index 012345678
-# CHECK: [0,0] DeeeeER . ldr w0, [sp]
-# CHECK-NEXT: [0,1] D====eER . add x0, x0, x0
-# CHECK-NEXT: [1,0] DeeeeE-R . ldr w0, [sp]
-# CHECK-NEXT: [1,1] D=====eER . add x0, x0, x0
-# CHECK-NEXT: [2,0] DeeeeE--R . ldr w0, [sp]
-# CHECK-NEXT: [2,1] D======eER. add x0, x0, x0
-# CHECK-NEXT: [3,0] D=eeeeE--R. ldr w0, [sp]
-# CHECK-NEXT: [3,1] D=======eER add x0, x0, x0
+# CHECK: [0,0] DeeeeER . ldr w0, [sp]
+# CHECK-NEXT: [0,1] D====eER. add x0, x0, x0
+# CHECK-NEXT: [1,0] DeeeeE-R. ldr w0, [sp]
+# CHECK-NEXT: [1,1] D====eER. add x0, x0, x0
+# CHECK-NEXT: [2,0] DeeeeE-R. ldr w0, [sp]
+# CHECK-NEXT: [2,1] D====eER. add x0, x0, x0
+# CHECK-NEXT: [3,0] D=eeeeER. ldr w0, [sp]
+# CHECK-NEXT: [3,1] D=====eER add x0, x0, x0
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -121,20 +120,20 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr w0, [sp]
-# CHECK-NEXT: 1. 4 6.5 0.0 0.0 add x0, x0, x0
-# CHECK-NEXT: 4 3.9 0.6 0.6 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 0.5 ldr w0, [sp]
+# CHECK-NEXT: 1. 4 5.3 0.0 0.0 add x0, x0, x0
+# CHECK-NEXT: 4 3.3 0.6 0.3 <total>
# CHECK: [1] Code Region - FPR8-bit
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 209
+# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 15
-# CHECK-NEXT: uOps Per Cycle: 0.96
-# CHECK-NEXT: IPC: 0.96
+# CHECK-NEXT: uOps Per Cycle: 4.55
+# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -176,17 +175,17 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: - - - - - - - - - - - 0.25 0.25 0.25 0.25 fadd d0, d0, d0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456
+# CHECK-NEXT: 01
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER . .. ldr b0, [sp]
-# CHECK-NEXT: [0,1] D======eeER .. fadd d0, d0, d0
-# CHECK-NEXT: [1,0] DeeeeeeE--R .. ldr b0, [sp]
-# CHECK-NEXT: [1,1] D========eeER .. fadd d0, d0, d0
-# CHECK-NEXT: [2,0] DeeeeeeE----R .. ldr b0, [sp]
-# CHECK-NEXT: [2,1] D==========eeER.. fadd d0, d0, d0
-# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ldr b0, [sp]
-# CHECK-NEXT: [3,1] D============eeER fadd d0, d0, d0
+# CHECK: [0,0] DeeeeeeER .. ldr b0, [sp]
+# CHECK-NEXT: [0,1] D======eeER. fadd d0, d0, d0
+# CHECK-NEXT: [1,0] DeeeeeeE--R. ldr b0, [sp]
+# CHECK-NEXT: [1,1] D======eeER. fadd d0, d0, d0
+# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr b0, [sp]
+# CHECK-NEXT: [2,1] D======eeER. fadd d0, d0, d0
+# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr b0, [sp]
+# CHECK-NEXT: [3,1] D=======eeER fadd d0, d0, d0
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -195,20 +194,20 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ldr b0, [sp]
-# CHECK-NEXT: 1. 4 10.0 0.0 0.0 fadd d0, d0, d0
-# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr b0, [sp]
+# CHECK-NEXT: 1. 4 7.3 0.0 0.0 fadd d0, d0, d0
+# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK: [2] Code Region - FPR16-bit
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 209
+# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 15
-# CHECK-NEXT: uOps Per Cycle: 0.96
-# CHECK-NEXT: IPC: 0.96
+# CHECK-NEXT: uOps Per Cycle: 4.55
+# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -250,17 +249,17 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: - - - - - - - - - - - 0.25 0.25 0.25 0.25 fadd d0, d0, d0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456
+# CHECK-NEXT: 01
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER . .. ldr h0, [sp]
-# CHECK-NEXT: [0,1] D======eeER .. fadd d0, d0, d0
-# CHECK-NEXT: [1,0] DeeeeeeE--R .. ldr h0, [sp]
-# CHECK-NEXT: [1,1] D========eeER .. fadd d0, d0, d0
-# CHECK-NEXT: [2,0] DeeeeeeE----R .. ldr h0, [sp]
-# CHECK-NEXT: [2,1] D==========eeER.. fadd d0, d0, d0
-# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ldr h0, [sp]
-# CHECK-NEXT: [3,1] D============eeER fadd d0, d0, d0
+# CHECK: [0,0] DeeeeeeER .. ldr h0, [sp]
+# CHECK-NEXT: [0,1] D======eeER. fadd d0, d0, d0
+# CHECK-NEXT: [1,0] DeeeeeeE--R. ldr h0, [sp]
+# CHECK-NEXT: [1,1] D======eeER. fadd d0, d0, d0
+# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr h0, [sp]
+# CHECK-NEXT: [2,1] D======eeER. fadd d0, d0, d0
+# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr h0, [sp]
+# CHECK-NEXT: [3,1] D=======eeER fadd d0, d0, d0
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -269,20 +268,20 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ldr h0, [sp]
-# CHECK-NEXT: 1. 4 10.0 0.0 0.0 fadd d0, d0, d0
-# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr h0, [sp]
+# CHECK-NEXT: 1. 4 7.3 0.0 0.0 fadd d0, d0, d0
+# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK: [3] Code Region - FPR32-bit
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 209
+# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 15
-# CHECK-NEXT: uOps Per Cycle: 0.96
-# CHECK-NEXT: IPC: 0.96
+# CHECK-NEXT: uOps Per Cycle: 4.55
+# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -324,17 +323,17 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: - - - - - - - - - - - 0.25 0.25 0.25 0.25 fadd d0, d0, d0
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456
+# CHECK-NEXT: 01
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER . .. ldr s0, [sp]
-# CHECK-NEXT: [0,1] D======eeER .. fadd d0, d0, d0
-# CHECK-NEXT: [1,0] DeeeeeeE--R .. ldr s0, [sp]
-# CHECK-NEXT: [1,1] D========eeER .. fadd d0, d0, d0
-# CHECK-NEXT: [2,0] DeeeeeeE----R .. ldr s0, [sp]
-# CHECK-NEXT: [2,1] D==========eeER.. fadd d0, d0, d0
-# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ldr s0, [sp]
-# CHECK-NEXT: [3,1] D============eeER fadd d0, d0, d0
+# CHECK: [0,0] DeeeeeeER .. ldr s0, [sp]
+# CHECK-NEXT: [0,1] D======eeER. fadd d0, d0, d0
+# CHECK-NEXT: [1,0] DeeeeeeE--R. ldr s0, [sp]
+# CHECK-NEXT: [1,1] D======eeER. fadd d0, d0, d0
+# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr s0, [sp]
+# CHECK-NEXT: [2,1] D======eeER. fadd d0, d0, d0
+# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr s0, [sp]
+# CHECK-NEXT: [3,1] D=======eeER fadd d0, d0, d0
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -343,20 +342,20 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ldr s0, [sp]
-# CHECK-NEXT: 1. 4 10.0 0.0 0.0 fadd d0, d0, d0
-# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr s0, [sp]
+# CHECK-NEXT: 1. 4 7.3 0.0 0.0 fadd d0, d0, d0
+# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK: [4] Code Region - SIMD64-bit-b
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 209
+# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 15
-# CHECK-NEXT: uOps Per Cycle: 0.96
-# CHECK-NEXT: IPC: 0.96
+# CHECK-NEXT: uOps Per Cycle: 4.55
+# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -398,17 +397,17 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: - - - - - - - - - - - 0.25 0.25 0.25 0.25 add v0.16b, v0.16b, v0.16b
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456
+# CHECK-NEXT: 01
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER . .. ld1 { v0.8b }, [sp]
-# CHECK-NEXT: [0,1] D======eeER .. add v0.16b, v0.16b, v0.16b
-# CHECK-NEXT: [1,0] DeeeeeeE--R .. ld1 { v0.8b }, [sp]
-# CHECK-NEXT: [1,1] D========eeER .. add v0.16b, v0.16b, v0.16b
-# CHECK-NEXT: [2,0] DeeeeeeE----R .. ld1 { v0.8b }, [sp]
-# CHECK-NEXT: [2,1] D==========eeER.. add v0.16b, v0.16b, v0.16b
-# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ld1 { v0.8b }, [sp]
-# CHECK-NEXT: [3,1] D============eeER add v0.16b, v0.16b, v0.16b
+# CHECK: [0,0] DeeeeeeER .. ld1 { v0.8b }, [sp]
+# CHECK-NEXT: [0,1] D======eeER. add v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: [1,0] DeeeeeeE--R. ld1 { v0.8b }, [sp]
+# CHECK-NEXT: [1,1] D======eeER. add v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.8b }, [sp]
+# CHECK-NEXT: [2,1] D======eeER. add v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.8b }, [sp]
+# CHECK-NEXT: [3,1] D=======eeER add v0.16b, v0.16b, v0.16b
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -417,20 +416,20 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ld1 { v0.8b }, [sp]
-# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add v0.16b, v0.16b, v0.16b
-# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.8b }, [sp]
+# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add v0.16b, v0.16b, v0.16b
+# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK: [5] Code Region - SIMD64-bit-h
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 209
+# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 15
-# CHECK-NEXT: uOps Per Cycle: 0.96
-# CHECK-NEXT: IPC: 0.96
+# CHECK-NEXT: uOps Per Cycle: 4.55
+# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -472,17 +471,17 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: - - - - - - - - - - - 0.25 0.25 0.25 0.25 add v0.8h, v0.8h, v0.8h
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456
+# CHECK-NEXT: 01
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER . .. ld1 { v0.4h }, [sp]
-# CHECK-NEXT: [0,1] D======eeER .. add v0.8h, v0.8h, v0.8h
-# CHECK-NEXT: [1,0] DeeeeeeE--R .. ld1 { v0.4h }, [sp]
-# CHECK-NEXT: [1,1] D========eeER .. add v0.8h, v0.8h, v0.8h
-# CHECK-NEXT: [2,0] DeeeeeeE----R .. ld1 { v0.4h }, [sp]
-# CHECK-NEXT: [2,1] D==========eeER.. add v0.8h, v0.8h, v0.8h
-# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ld1 { v0.4h }, [sp]
-# CHECK-NEXT: [3,1] D============eeER add v0.8h, v0.8h, v0.8h
+# CHECK: [0,0] DeeeeeeER .. ld1 { v0.4h }, [sp]
+# CHECK-NEXT: [0,1] D======eeER. add v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: [1,0] DeeeeeeE--R. ld1 { v0.4h }, [sp]
+# CHECK-NEXT: [1,1] D======eeER. add v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.4h }, [sp]
+# CHECK-NEXT: [2,1] D======eeER. add v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.4h }, [sp]
+# CHECK-NEXT: [3,1] D=======eeER add v0.8h, v0.8h, v0.8h
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -491,20 +490,20 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ld1 { v0.4h }, [sp]
-# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add v0.8h, v0.8h, v0.8h
-# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.4h }, [sp]
+# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add v0.8h, v0.8h, v0.8h
+# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK: [6] Code Region - SIMD64-bit-s
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 209
+# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 15
-# CHECK-NEXT: uOps Per Cycle: 0.96
-# CHECK-NEXT: IPC: 0.96
+# CHECK-NEXT: uOps Per Cycle: 4.55
+# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -546,17 +545,17 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: - - - - - - - - - - - 0.25 0.25 0.25 0.25 add v0.4s, v0.4s, v0.4s
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456
+# CHECK-NEXT: 01
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER . .. ld1 { v0.2s }, [sp]
-# CHECK-NEXT: [0,1] D======eeER .. add v0.4s, v0.4s, v0.4s
-# CHECK-NEXT: [1,0] DeeeeeeE--R .. ld1 { v0.2s }, [sp]
-# CHECK-NEXT: [1,1] D========eeER .. add v0.4s, v0.4s, v0.4s
-# CHECK-NEXT: [2,0] DeeeeeeE----R .. ld1 { v0.2s }, [sp]
-# CHECK-NEXT: [2,1] D==========eeER.. add v0.4s, v0.4s, v0.4s
-# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ld1 { v0.2s }, [sp]
-# CHECK-NEXT: [3,1] D============eeER add v0.4s, v0.4s, v0.4s
+# CHECK: [0,0] DeeeeeeER .. ld1 { v0.2s }, [sp]
+# CHECK-NEXT: [0,1] D======eeER. add v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: [1,0] DeeeeeeE--R. ld1 { v0.2s }, [sp]
+# CHECK-NEXT: [1,1] D======eeER. add v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.2s }, [sp]
+# CHECK-NEXT: [2,1] D======eeER. add v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.2s }, [sp]
+# CHECK-NEXT: [3,1] D=======eeER add v0.4s, v0.4s, v0.4s
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -565,20 +564,20 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ld1 { v0.2s }, [sp]
-# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add v0.4s, v0.4s, v0.4s
-# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.2s }, [sp]
+# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add v0.4s, v0.4s, v0.4s
+# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK: [7] Code Region - SIMD64-bit-d
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 209
+# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 15
-# CHECK-NEXT: uOps Per Cycle: 0.96
-# CHECK-NEXT: IPC: 0.96
+# CHECK-NEXT: uOps Per Cycle: 4.55
+# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -620,17 +619,17 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: - - - - - - - - - - - 0.25 0.25 0.25 0.25 add v0.2d, v0.2d, v0.2d
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456
+# CHECK-NEXT: 01
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER . .. ld1 { v0.1d }, [sp]
-# CHECK-NEXT: [0,1] D======eeER .. add v0.2d, v0.2d, v0.2d
-# CHECK-NEXT: [1,0] DeeeeeeE--R .. ld1 { v0.1d }, [sp]
-# CHECK-NEXT: [1,1] D========eeER .. add v0.2d, v0.2d, v0.2d
-# CHECK-NEXT: [2,0] DeeeeeeE----R .. ld1 { v0.1d }, [sp]
-# CHECK-NEXT: [2,1] D==========eeER.. add v0.2d, v0.2d, v0.2d
-# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ld1 { v0.1d }, [sp]
-# CHECK-NEXT: [3,1] D============eeER add v0.2d, v0.2d, v0.2d
+# CHECK: [0,0] DeeeeeeER .. ld1 { v0.1d }, [sp]
+# CHECK-NEXT: [0,1] D======eeER. add v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: [1,0] DeeeeeeE--R. ld1 { v0.1d }, [sp]
+# CHECK-NEXT: [1,1] D======eeER. add v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.1d }, [sp]
+# CHECK-NEXT: [2,1] D======eeER. add v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.1d }, [sp]
+# CHECK-NEXT: [3,1] D=======eeER add v0.2d, v0.2d, v0.2d
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -639,9 +638,9 @@ add v0.16b, v0.16b, v0.16b
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ld1 { v0.1d }, [sp]
-# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add v0.2d, v0.2d, v0.2d
-# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.1d }, [sp]
+# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add v0.2d, v0.2d, v0.2d
+# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK: [8] Code Region - ins
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-clear-upper-regs.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-clear-upper-regs.s
index c15ed9230edc90..fd2083dc1277a0 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-clear-upper-regs.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-clear-upper-regs.s
@@ -55,12 +55,12 @@ add z0.s, z0.s, z0.s
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 209
+# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 16
-# CHECK-NEXT: uOps Per Cycle: 0.96
-# CHECK-NEXT: IPC: 0.96
+# CHECK-NEXT: uOps Per Cycle: 4.55
+# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -104,17 +104,17 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add z0.d, z0.d, z0.d
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456
+# CHECK-NEXT: 01
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER . .. ldr b0, [sp]
-# CHECK-NEXT: [0,1] D======eeER .. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [1,0] DeeeeeeE--R .. ldr b0, [sp]
-# CHECK-NEXT: [1,1] D========eeER .. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [2,0] DeeeeeeE----R .. ldr b0, [sp]
-# CHECK-NEXT: [2,1] D==========eeER.. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ldr b0, [sp]
-# CHECK-NEXT: [3,1] D============eeER add z0.d, z0.d, z0.d
+# CHECK: [0,0] DeeeeeeER .. ldr b0, [sp]
+# CHECK-NEXT: [0,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,0] DeeeeeeE--R. ldr b0, [sp]
+# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr b0, [sp]
+# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr b0, [sp]
+# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -123,20 +123,20 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ldr b0, [sp]
-# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add z0.d, z0.d, z0.d
-# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr b0, [sp]
+# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
+# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK: [1] Code Region - FPR16-bit
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 209
+# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 16
-# CHECK-NEXT: uOps Per Cycle: 0.96
-# CHECK-NEXT: IPC: 0.96
+# CHECK-NEXT: uOps Per Cycle: 4.55
+# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -180,17 +180,17 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add z0.d, z0.d, z0.d
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456
+# CHECK-NEXT: 01
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER . .. ldr h0, [sp]
-# CHECK-NEXT: [0,1] D======eeER .. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [1,0] DeeeeeeE--R .. ldr h0, [sp]
-# CHECK-NEXT: [1,1] D========eeER .. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [2,0] DeeeeeeE----R .. ldr h0, [sp]
-# CHECK-NEXT: [2,1] D==========eeER.. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ldr h0, [sp]
-# CHECK-NEXT: [3,1] D============eeER add z0.d, z0.d, z0.d
+# CHECK: [0,0] DeeeeeeER .. ldr h0, [sp]
+# CHECK-NEXT: [0,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,0] DeeeeeeE--R. ldr h0, [sp]
+# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr h0, [sp]
+# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr h0, [sp]
+# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -199,20 +199,20 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ldr h0, [sp]
-# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add z0.d, z0.d, z0.d
-# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr h0, [sp]
+# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
+# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK: [2] Code Region - FPR32-bit
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 209
+# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 16
-# CHECK-NEXT: uOps Per Cycle: 0.96
-# CHECK-NEXT: IPC: 0.96
+# CHECK-NEXT: uOps Per Cycle: 4.55
+# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -256,17 +256,17 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add z0.d, z0.d, z0.d
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456
+# CHECK-NEXT: 01
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER . .. ldr s0, [sp]
-# CHECK-NEXT: [0,1] D======eeER .. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [1,0] DeeeeeeE--R .. ldr s0, [sp]
-# CHECK-NEXT: [1,1] D========eeER .. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [2,0] DeeeeeeE----R .. ldr s0, [sp]
-# CHECK-NEXT: [2,1] D==========eeER.. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ldr s0, [sp]
-# CHECK-NEXT: [3,1] D============eeER add z0.d, z0.d, z0.d
+# CHECK: [0,0] DeeeeeeER .. ldr s0, [sp]
+# CHECK-NEXT: [0,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,0] DeeeeeeE--R. ldr s0, [sp]
+# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr s0, [sp]
+# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr s0, [sp]
+# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -275,20 +275,20 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ldr s0, [sp]
-# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add z0.d, z0.d, z0.d
-# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr s0, [sp]
+# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
+# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK: [3] Code Region - FPR64-bit
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 209
+# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 16
-# CHECK-NEXT: uOps Per Cycle: 0.96
-# CHECK-NEXT: IPC: 0.96
+# CHECK-NEXT: uOps Per Cycle: 4.55
+# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -332,17 +332,17 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add z0.d, z0.d, z0.d
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456
+# CHECK-NEXT: 01
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER . .. ldr d0, [sp]
-# CHECK-NEXT: [0,1] D======eeER .. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [1,0] DeeeeeeE--R .. ldr d0, [sp]
-# CHECK-NEXT: [1,1] D========eeER .. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [2,0] DeeeeeeE----R .. ldr d0, [sp]
-# CHECK-NEXT: [2,1] D==========eeER.. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ldr d0, [sp]
-# CHECK-NEXT: [3,1] D============eeER add z0.d, z0.d, z0.d
+# CHECK: [0,0] DeeeeeeER .. ldr d0, [sp]
+# CHECK-NEXT: [0,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,0] DeeeeeeE--R. ldr d0, [sp]
+# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr d0, [sp]
+# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr d0, [sp]
+# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -351,20 +351,20 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ldr d0, [sp]
-# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add z0.d, z0.d, z0.d
-# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr d0, [sp]
+# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
+# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK: [4] Code Region - FPR128-bit
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 209
+# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 16
-# CHECK-NEXT: uOps Per Cycle: 0.96
-# CHECK-NEXT: IPC: 0.96
+# CHECK-NEXT: uOps Per Cycle: 4.55
+# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -408,17 +408,17 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add z0.d, z0.d, z0.d
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456
+# CHECK-NEXT: 01
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER . .. ldr q0, [sp]
-# CHECK-NEXT: [0,1] D======eeER .. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [1,0] DeeeeeeE--R .. ldr q0, [sp]
-# CHECK-NEXT: [1,1] D========eeER .. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [2,0] DeeeeeeE----R .. ldr q0, [sp]
-# CHECK-NEXT: [2,1] D==========eeER.. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ldr q0, [sp]
-# CHECK-NEXT: [3,1] D============eeER add z0.d, z0.d, z0.d
+# CHECK: [0,0] DeeeeeeER .. ldr q0, [sp]
+# CHECK-NEXT: [0,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,0] DeeeeeeE--R. ldr q0, [sp]
+# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [2,0] DeeeeeeE--R. ldr q0, [sp]
+# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [3,0] D=eeeeeeE-R. ldr q0, [sp]
+# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -427,20 +427,20 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ldr q0, [sp]
-# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add z0.d, z0.d, z0.d
-# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ldr q0, [sp]
+# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
+# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK: [5] Code Region - SIMD64-bit-b
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 209
+# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 16
-# CHECK-NEXT: uOps Per Cycle: 0.96
-# CHECK-NEXT: IPC: 0.96
+# CHECK-NEXT: uOps Per Cycle: 4.55
+# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -484,17 +484,17 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add z0.d, z0.d, z0.d
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456
+# CHECK-NEXT: 01
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER . .. ld1 { v0.8b }, [sp]
-# CHECK-NEXT: [0,1] D======eeER .. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [1,0] DeeeeeeE--R .. ld1 { v0.8b }, [sp]
-# CHECK-NEXT: [1,1] D========eeER .. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [2,0] DeeeeeeE----R .. ld1 { v0.8b }, [sp]
-# CHECK-NEXT: [2,1] D==========eeER.. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ld1 { v0.8b }, [sp]
-# CHECK-NEXT: [3,1] D============eeER add z0.d, z0.d, z0.d
+# CHECK: [0,0] DeeeeeeER .. ld1 { v0.8b }, [sp]
+# CHECK-NEXT: [0,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,0] DeeeeeeE--R. ld1 { v0.8b }, [sp]
+# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.8b }, [sp]
+# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.8b }, [sp]
+# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -503,20 +503,20 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ld1 { v0.8b }, [sp]
-# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add z0.d, z0.d, z0.d
-# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.8b }, [sp]
+# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
+# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK: [6] Code Region - SIMD64-bit-h
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 209
+# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 16
-# CHECK-NEXT: uOps Per Cycle: 0.96
-# CHECK-NEXT: IPC: 0.96
+# CHECK-NEXT: uOps Per Cycle: 4.55
+# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -560,17 +560,17 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add z0.d, z0.d, z0.d
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456
+# CHECK-NEXT: 01
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER . .. ld1 { v0.4h }, [sp]
-# CHECK-NEXT: [0,1] D======eeER .. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [1,0] DeeeeeeE--R .. ld1 { v0.4h }, [sp]
-# CHECK-NEXT: [1,1] D========eeER .. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [2,0] DeeeeeeE----R .. ld1 { v0.4h }, [sp]
-# CHECK-NEXT: [2,1] D==========eeER.. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ld1 { v0.4h }, [sp]
-# CHECK-NEXT: [3,1] D============eeER add z0.d, z0.d, z0.d
+# CHECK: [0,0] DeeeeeeER .. ld1 { v0.4h }, [sp]
+# CHECK-NEXT: [0,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,0] DeeeeeeE--R. ld1 { v0.4h }, [sp]
+# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.4h }, [sp]
+# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.4h }, [sp]
+# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -579,20 +579,20 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ld1 { v0.4h }, [sp]
-# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add z0.d, z0.d, z0.d
-# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.4h }, [sp]
+# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
+# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK: [7] Code Region - SIMD64-bit-s
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 209
+# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 16
-# CHECK-NEXT: uOps Per Cycle: 0.96
-# CHECK-NEXT: IPC: 0.96
+# CHECK-NEXT: uOps Per Cycle: 4.55
+# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -636,17 +636,17 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add z0.d, z0.d, z0.d
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456
+# CHECK-NEXT: 01
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER . .. ld1 { v0.2s }, [sp]
-# CHECK-NEXT: [0,1] D======eeER .. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [1,0] DeeeeeeE--R .. ld1 { v0.2s }, [sp]
-# CHECK-NEXT: [1,1] D========eeER .. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [2,0] DeeeeeeE----R .. ld1 { v0.2s }, [sp]
-# CHECK-NEXT: [2,1] D==========eeER.. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ld1 { v0.2s }, [sp]
-# CHECK-NEXT: [3,1] D============eeER add z0.d, z0.d, z0.d
+# CHECK: [0,0] DeeeeeeER .. ld1 { v0.2s }, [sp]
+# CHECK-NEXT: [0,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,0] DeeeeeeE--R. ld1 { v0.2s }, [sp]
+# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.2s }, [sp]
+# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.2s }, [sp]
+# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -655,20 +655,20 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ld1 { v0.2s }, [sp]
-# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add z0.d, z0.d, z0.d
-# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.2s }, [sp]
+# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
+# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK: [8] Code Region - SIMD64-bit-d
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 209
+# CHECK-NEXT: Total Cycles: 44
# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 16
-# CHECK-NEXT: uOps Per Cycle: 0.96
-# CHECK-NEXT: IPC: 0.96
+# CHECK-NEXT: uOps Per Cycle: 4.55
+# CHECK-NEXT: IPC: 4.55
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -712,17 +712,17 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: - - - - - - - - - - - - - 0.25 0.25 0.25 0.25 add z0.d, z0.d, z0.d
# CHECK: Timeline view:
-# CHECK-NEXT: 0123456
+# CHECK-NEXT: 01
# CHECK-NEXT: Index 0123456789
-# CHECK: [0,0] DeeeeeeER . .. ld1 { v0.1d }, [sp]
-# CHECK-NEXT: [0,1] D======eeER .. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [1,0] DeeeeeeE--R .. ld1 { v0.1d }, [sp]
-# CHECK-NEXT: [1,1] D========eeER .. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [2,0] DeeeeeeE----R .. ld1 { v0.1d }, [sp]
-# CHECK-NEXT: [2,1] D==========eeER.. add z0.d, z0.d, z0.d
-# CHECK-NEXT: [3,0] D=eeeeeeE-----R.. ld1 { v0.1d }, [sp]
-# CHECK-NEXT: [3,1] D============eeER add z0.d, z0.d, z0.d
+# CHECK: [0,0] DeeeeeeER .. ld1 { v0.1d }, [sp]
+# CHECK-NEXT: [0,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [1,0] DeeeeeeE--R. ld1 { v0.1d }, [sp]
+# CHECK-NEXT: [1,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [2,0] DeeeeeeE--R. ld1 { v0.1d }, [sp]
+# CHECK-NEXT: [2,1] D======eeER. add z0.d, z0.d, z0.d
+# CHECK-NEXT: [3,0] D=eeeeeeE-R. ld1 { v0.1d }, [sp]
+# CHECK-NEXT: [3,1] D=======eeER add z0.d, z0.d, z0.d
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -731,9 +731,9 @@ add z0.s, z0.s, z0.s
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 4 1.3 1.3 2.8 ld1 { v0.1d }, [sp]
-# CHECK-NEXT: 1. 4 10.0 0.0 0.0 add z0.d, z0.d, z0.d
-# CHECK-NEXT: 4 5.6 0.6 1.4 <total>
+# CHECK-NEXT: 0. 4 1.3 1.3 1.3 ld1 { v0.1d }, [sp]
+# CHECK-NEXT: 1. 4 7.3 0.0 0.0 add z0.d, z0.d, z0.d
+# CHECK-NEXT: 4 4.3 0.6 0.6 <total>
# CHECK: [9] Code Region - insr
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index be2a2b3884c73b..a6f87119aca5ba 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -953,7 +953,7 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS) {
OS << "extern const MCRegisterDesc " << TargetName
<< "RegDesc[] = { // Descriptors\n";
- OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0, 0 },\n";
+ OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0, 0, 0 },\n";
// Emit the register descriptors now.
i = 0;
@@ -968,8 +968,8 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS) {
<< DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i])
<< ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", "
<< (Offset << RegUnitBits | FirstRU) << ", "
- << LaneMaskSeqs.get(RegUnitLaneMasks[i]) << ", " << Reg.Constant
- << " },\n";
+ << LaneMaskSeqs.get(RegUnitLaneMasks[i]) << ", " << Reg.Constant << ", "
+ << Reg.Artificial << " },\n";
++i;
}
OS << "};\n\n"; // End of register descriptors...
>From 4ef35e2d76fff1e642e67fb12a5755eae6d1417f Mon Sep 17 00:00:00 2001
From: Sander de Smalen <sander.desmalen at arm.com>
Date: Tue, 12 Nov 2024 08:32:13 +0000
Subject: [PATCH 7/7] Clarify meaning of artificial
---
llvm/include/llvm/MC/MCRegisterInfo.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/llvm/include/llvm/MC/MCRegisterInfo.h b/llvm/include/llvm/MC/MCRegisterInfo.h
index 0ddda5b53b5f4e..6f202ba199e052 100644
--- a/llvm/include/llvm/MC/MCRegisterInfo.h
+++ b/llvm/include/llvm/MC/MCRegisterInfo.h
@@ -399,7 +399,9 @@ class MCRegisterInfo {
/// Returns true if the given register is constant.
bool isConstant(MCRegister RegNo) const { return get(RegNo).IsConstant; }
- /// Returns true if the given register is artificial.
+ /// Returns true if the given register is artificial, which means it represents
+ /// a regunit that is not separately addressable but still needs to be modelled,
+ /// such as the top 16-bits of a 32-bit GPR.
bool isArtificial(MCRegister RegNo) const { return get(RegNo).IsArtificial; }
/// Return the number of registers this target has (useful for
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