[llvm] [AArch64] Define high bits of FPR and GPR registers (take 2) (PR #114827)

[David Green via llvm-commits]

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@@ -17,13 +17,18 @@
 # CHECK-NEXT:   Single Issue       : false;
 # CHECK-NEXT: SU(1):   renamable $z1 = LD1H renamable $p0, renamable $x2, renamable $x10 :: (load unknown-size, align 1)
 # CHECK-NEXT:   # preds left       : 0
-# CHECK-NEXT:   # succs left       : 4
+# CHECK-NEXT:   # succs left       : 9
 # CHECK-NEXT:   # rdefs left       : 0
 # CHECK-NEXT:   Latency            : 3
 # CHECK-NEXT:   Depth              : 0
 # CHECK-NEXT:   Height             : 7
 # CHECK-NEXT:   Successors:
 # CHECK-NEXT:     SU(7): Out  Latency=1
+# CHECK-NEXT:     SU(7): Out  Latency=1
----------------
davemgreen wrote:

Does this happen just for bundles or for other instructions? I was wondering if it was worth filtering out Artificial dependencies as they should be redundant, I believe? It might not matter too much if it is only bundles, as it doesn't seem to be doing any harm and they come up less often so would have less of a compile-time overhead to have so many deps.

https://github.com/llvm/llvm-project/pull/114827