[llvm] 60ea60e - [RISCV] Fix some isel patterns that used a type where we normally put a regclass. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-11-08T18:11:39-08:00
New Revision: 60ea60e36eb6de19e8e509e5b50a390e95801321

URL: https://github.com/llvm/llvm-project/commit/60ea60e36eb6de19e8e509e5b50a390e95801321
DIFF: https://github.com/llvm/llvm-project/commit/60ea60e36eb6de19e8e509e5b50a390e95801321.diff

LOG: [RISCV] Fix some isel patterns that used a type where we normally put a regclass. NFC

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVGISel.td
    llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index c0af1d60cb6015..83018f28176564 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -264,7 +264,7 @@ def : Pat<(i32 (xor GPR:$rs1, (not GPR:$rs2))), (XNOR GPR:$rs1, GPR:$rs2)>;
 } // Predicates = [HasStdExtZbbOrZbkb, IsRV64]
 
 let Predicates = [HasStdExtZba, IsRV64] in {
-def : Pat<(shl (i64 (zext i32:$rs1)), uimm5:$shamt),
+def : Pat<(shl (i64 (zext GPR:$rs1)), uimm5:$shamt),
           (SLLI_UW GPR:$rs1, uimm5:$shamt)>;
 
 def : Pat<(i64 (add_like_non_imm12 (zext GPR:$rs1), GPR:$rs2)),

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 0df0187d40889b..021c4b3b724b02 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -25,6 +25,7 @@ def rvv_vnot : PatFrag<(ops node:$in),
                        (xor node:$in, (riscv_vmset_vl (XLenVT srcvalue)))>;
 
 multiclass VPatUSLoadStoreSDNode<ValueType type,
+                                 RegisterClass regclass,
                                  int log2sew,
                                  LMULInfo vlmul,
                                  OutPatFrag avl,
@@ -37,7 +38,7 @@ multiclass VPatUSLoadStoreSDNode<ValueType type,
             (load_instr (type (IMPLICIT_DEF)), GPR:$rs1, avl,
                         log2sew, TA_MA)>;
   // Store
-  def : Pat<(store type:$rs2, (XLenVT GPR:$rs1)),
+  def : Pat<(store (type regclass:$rs2), (XLenVT GPR:$rs1)),
             (store_instr reg_class:$rs2, GPR:$rs1, avl, log2sew)>;
 }
 
@@ -49,7 +50,7 @@ multiclass VPatUSLoadStoreMaskSDNode<MTypeInfo m> {
             (load_instr (m.Mask (IMPLICIT_DEF)), GPR:$rs1, m.AVL,
                          m.Log2SEW, TA_MA)>;
   // Store
-  def : Pat<(store m.Mask:$rs2, GPR:$rs1),
+  def : Pat<(store (m.Mask VR:$rs2), GPR:$rs1),
             (store_instr VR:$rs2, GPR:$rs1, m.AVL, m.Log2SEW)>;
 }
 
@@ -884,7 +885,7 @@ multiclass VPatAVGADD_VV_VX_RM<SDNode vop, int vxrm, string suffix = ""> {
 foreach vti = AllVectors in
   let Predicates = !if(!eq(vti.Scalar, f16), [HasVInstructionsF16Minimal],
                        GetVTypePredicates<vti>.Predicates) in 
-  defm : VPatUSLoadStoreSDNode<vti.Vector, vti.Log2SEW, vti.LMul,
+  defm : VPatUSLoadStoreSDNode<vti.Vector, vti.RegClass, vti.Log2SEW, vti.LMul,
                                vti.AVL, vti.RegClass>;
 foreach mti = AllMasks in
   let Predicates = [HasVInstructions] in