[llvm] [RISCV] Add a feature to indicate the whole register move won't trap on vill (PR #114942)

Philip Reames via llvm-commits llvm-commits at lists.llvm.org
Fri Nov 8 10:03:55 PST 2024


preames wrote:

This got discussed at the RISCV sync up yesterday, but I wanted to record a quick summary.  We would like to not see a forking in code generation based on this property.  There is a desire to see if we can fix this through either a psabi change or a compiler change in a manner which doesn't impose a performance hit.  If we can, a change like this is undesirable.  If we can't, we will revisit.  

https://github.com/llvm/llvm-project/pull/114942


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