[llvm] 3797daa - [AArch64] Create set.fpmr intrinsic and assembly lowering (#114248)

[via llvm-commits]

Author: Lukacma
Date: 2024-11-08T12:18:38Z
New Revision: 3797daa5448f3471c0d7d1c67838922a83a06fa1

URL: https://github.com/llvm/llvm-project/commit/3797daa5448f3471c0d7d1c67838922a83a06fa1
DIFF: https://github.com/llvm/llvm-project/commit/3797daa5448f3471c0d7d1c67838922a83a06fa1.diff

LOG: [AArch64] Create set.fpmr intrinsic and assembly lowering (#114248)

This patch introduces new llvm.set.fpmr intrinsics for setting value in
FPMR register and adds its lowering to series of read-compare-write
instructions. This intrinsic will be generated during lowering of FP8 C
intrinsics into LLVM-IR introduced in later patch.

***This is an experimental implementation of handling fp8 intriniscs and
is likely to change in the future.***

Added: 
    

Modified: 
    llvm/include/llvm/IR/IntrinsicsAArch64.td
    llvm/lib/Target/AArch64/AArch64InstrInfo.td
    llvm/test/CodeGen/AArch64/arm64-fpenv.ll

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td
index 594069c619ceb0..6a09a8647096f9 100644
--- a/llvm/include/llvm/IR/IntrinsicsAArch64.td
+++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td
@@ -771,6 +771,8 @@ let TargetPrefix = "aarch64" in {
     : DefaultAttrsIntrinsic<[], [llvm_i64_ty], [IntrNoMem, IntrHasSideEffects]>;
   class RNDR_Intrinsic
     : DefaultAttrsIntrinsic<[llvm_i64_ty, llvm_i1_ty], [], [IntrNoMem, IntrHasSideEffects]>;
+  class FPMR_Set_Intrinsic
+    : DefaultAttrsIntrinsic<[], [llvm_i64_ty], [IntrInaccessibleMemOnly]>; 
 }
 
 // FP environment registers.
@@ -778,6 +780,7 @@ def int_aarch64_get_fpcr : FPENV_Get_Intrinsic;
 def int_aarch64_set_fpcr : FPENV_Set_Intrinsic;
 def int_aarch64_get_fpsr : FPENV_Get_Intrinsic;
 def int_aarch64_set_fpsr : FPENV_Set_Intrinsic;
+def int_aarch64_set_fpmr : FPMR_Set_Intrinsic;
 
 // Armv8.5-A Random number generation intrinsics
 def int_aarch64_rndr : RNDR_Intrinsic;

diff  --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 5f1805ca3aa7c4..a31fd6c4b86a8a 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -2157,6 +2157,12 @@ def MSR_FPSR : Pseudo<(outs), (ins GPR64:$val),
                PseudoInstExpansion<(MSR 0xda21, GPR64:$val)>,
                Sched<[WriteSys]>;
 
+let Defs = [FPMR] in
+def MSR_FPMR : Pseudo<(outs), (ins GPR64:$val),
+                      [(int_aarch64_set_fpmr i64:$val)]>,
+               PseudoInstExpansion<(MSR 0xda22, GPR64:$val)>,
+               Sched<[WriteSys]>;
+
 // Generic system instructions
 def SYSxt  : SystemXtI<0, "sys">;
 def SYSLxt : SystemLXtI<1, "sysl">;

diff  --git a/llvm/test/CodeGen/AArch64/arm64-fpenv.ll b/llvm/test/CodeGen/AArch64/arm64-fpenv.ll
index 030809caee3394..412f89ae674399 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fpenv.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fpenv.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64 -verify-machineinstrs < %s | FileCheck %s
 
 define i64 @get_fpcr() #0 {
 ; CHECK-LABEL: get_fpcr:
@@ -37,6 +37,15 @@ define void @set_fpsr(i64 %sr) {
   ret void
 }
 
+define void @set_fpmr(i64 %sr) {
+; CHECK-LABEL: set_fpmr:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    msr FPMR, x0
+; CHECK-NEXT:    ret
+    call void @llvm.aarch64.set.fpmr(i64 %sr)
+    ret void
+}
+
 declare i64 @llvm.aarch64.get.fpcr()
 declare void @llvm.aarch64.set.fpcr(i64)
 declare i64 @llvm.aarch64.get.fpsr()