[llvm] [RISCV] Only allow 5 bit shift amounts in disassembler for RV32. (PR #115432)

Pengcheng Wang via llvm-commits llvm-commits at lists.llvm.org
Thu Nov 7 23:20:37 PST 2024

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https://github.com/wangpc-pp approved this pull request.


https://github.com/llvm/llvm-project/pull/115432

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