[llvm] [RISCV] Only allow 5 bit shift amounts in disassembler for RV32. (PR #115432)

[Yingwei Zheng via llvm-commits]

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@@ -314,6 +314,20 @@ static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm,
   return MCDisassembler::Success;
 }
 
+static DecodeStatus decodeUImmLog2XLenOperand(MCInst &Inst, uint32_t Imm,
+                                              int64_t Address,
+                                              const MCDisassembler *Decoder) {
+  assert(isUInt<6>(Imm) && "Invalid immediate");
+
+  if (!Decoder->getSubtargetInfo().hasFeature(RISCV::Feature64Bit) &&
+      !isUInt<5>(Imm))
+    return MCDisassembler::Fail;
+  ;
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dtcxzyw wrote:

```suggestion
```


https://github.com/llvm/llvm-project/pull/115432