[llvm] [AMDGPU][MIR] Serialize NumPhysicalVGPRSpillLanes (PR #115291)

[LLVM Continuous Integration via llvm-commits]

llvm-ci wrote:

LLVM Buildbot has detected a new failure on builder `ml-opt-rel-x86-64` running on `ml-opt-rel-x86-64-b1` while building `llvm` at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/185/builds/8091

<details>
<summary>Here is the relevant piece of the build log for the reference</summary>

```
Step 6 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll' FAILED ********************
Exit Code: 1

Command Output (stderr):
--
RUN: at line 1: /b/ml-opt-rel-x86-64-b1/build/bin/llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -amdgpu-spill-sgpr-to-vgpr=0 -stop-after prologepilog -verify-machineinstrs /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll -o - | /b/ml-opt-rel-x86-64-b1/build/bin/FileCheck -check-prefix=AFTER-PEI /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
+ /b/ml-opt-rel-x86-64-b1/build/bin/llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -amdgpu-spill-sgpr-to-vgpr=0 -stop-after prologepilog -verify-machineinstrs /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll -o -
+ /b/ml-opt-rel-x86-64-b1/build/bin/FileCheck -check-prefix=AFTER-PEI /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
/b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll:41:19: error: AFTER-PEI-NEXT: is not on the line after the previous match
; AFTER-PEI-NEXT: scavengeFI: '%stack.3'
                  ^
<stdin>:149:2: note: 'next' match was here
 scavengeFI: '%stack.3'
 ^
<stdin>:147:14: note: previous match ended here
 occupancy: 5
             ^
<stdin>:148:1: note: non-matching line after previous match is here
 numPhysicalVGPRSpillLanes: 0
^

Input file: <stdin>
Check file: /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll

-dump-input=help explains the following input dump.

Input was:
<<<<<<
         .
         .
         .
       144:  fp64-fp16-input-denormals: true 
       145:  fp64-fp16-output-denormals: true 
       146:  highBitsOf32BitAddress: 0 
       147:  occupancy: 5 
       148:  numPhysicalVGPRSpillLanes: 0 
       149:  scavengeFI: '%stack.3' 
next:41      !~~~~~~~~~~~~~~~~~~~~~  error: match on wrong line
       150:  vgprForAGPRCopy: '' 
       151:  sgprForEXECCopy: '' 
       152:  longBranchReservedReg: '' 
       153:  hasInitWholeWave: false 
       154: body: | 
         .
         .
         .
>>>>>>

--

...

```

</details>

https://github.com/llvm/llvm-project/pull/115291