[llvm] [NFC][PowerPC] Add getScalarIntVT to return MVT based on arch (PR #115203)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 6 12:02:49 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-powerpc
Author: Lei Huang (lei137)
<details>
<summary>Changes</summary>
Add `getScalarIntVT()` to return scalar int VT based on if arch is 32 or 64bit.
---
Full diff: https://github.com/llvm/llvm-project/pull/115203.diff
3 Files Affected:
- (modified) llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (+2-2)
- (modified) llvm/lib/Target/PowerPC/PPCISelLowering.cpp (+34-45)
- (modified) llvm/lib/Target/PowerPC/PPCSubtarget.h (+5-3)
``````````diff
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 1dd5c5e04d2132..a4d818028c89d5 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -6176,7 +6176,7 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
SDValue GA = N->getOperand(0);
SDValue TOCbase = N->getOperand(1);
- EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
+ EVT VT = Subtarget->getScalarIntVT();
SDNode *Tmp = CurDAG->getMachineNode(
isPPC64 ? PPC::ADDIStocHA8 : PPC::ADDIStocHA, dl, VT, TOCbase, GA);
@@ -6309,7 +6309,7 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
SDValue ZeroReg =
CurDAG->getRegister(Subtarget->isPPC64() ? PPC::ZERO8 : PPC::ZERO,
- Subtarget->isPPC64() ? MVT::i64 : MVT::i32);
+ Subtarget->getScalarIntVT());
unsigned LIOpcode = Subtarget->isPPC64() ? PPC::LI8 : PPC::LI;
// v16i8 LD_SPLAT addr
// ======>
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index ec4f8f4be425ed..8a4bfbf33bfad7 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -183,6 +183,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
// arguments are at least 4/8 bytes aligned.
bool isPPC64 = Subtarget.isPPC64();
setMinStackArgumentAlignment(isPPC64 ? Align(8) : Align(4));
+ const MVT RegVT = Subtarget.getScalarIntVT();
// Set up the register classes.
addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
@@ -198,7 +199,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
}
}
- setOperationAction(ISD::UADDO, isPPC64 ? MVT::i64 : MVT::i32, Custom);
+ setOperationAction(ISD::UADDO, RegVT, Custom);
// Match BITREVERSE to customized fast code sequence in the td file.
setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
@@ -268,32 +269,24 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
if (isPPC64 || Subtarget.hasFPCVT()) {
setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i1, Promote);
- AddPromotedToType(ISD::STRICT_SINT_TO_FP, MVT::i1,
- isPPC64 ? MVT::i64 : MVT::i32);
+ AddPromotedToType(ISD::STRICT_SINT_TO_FP, MVT::i1, RegVT);
setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i1, Promote);
- AddPromotedToType(ISD::STRICT_UINT_TO_FP, MVT::i1,
- isPPC64 ? MVT::i64 : MVT::i32);
+ AddPromotedToType(ISD::STRICT_UINT_TO_FP, MVT::i1, RegVT);
setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
- AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
- isPPC64 ? MVT::i64 : MVT::i32);
+ AddPromotedToType(ISD::SINT_TO_FP, MVT::i1, RegVT);
setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
- AddPromotedToType(ISD::UINT_TO_FP, MVT::i1,
- isPPC64 ? MVT::i64 : MVT::i32);
+ AddPromotedToType(ISD::UINT_TO_FP, MVT::i1, RegVT);
setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i1, Promote);
- AddPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::i1,
- isPPC64 ? MVT::i64 : MVT::i32);
+ AddPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::i1, RegVT);
setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i1, Promote);
- AddPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::i1,
- isPPC64 ? MVT::i64 : MVT::i32);
+ AddPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::i1, RegVT);
setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
- AddPromotedToType(ISD::FP_TO_SINT, MVT::i1,
- isPPC64 ? MVT::i64 : MVT::i32);
+ AddPromotedToType(ISD::FP_TO_SINT, MVT::i1, RegVT);
setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
- AddPromotedToType(ISD::FP_TO_UINT, MVT::i1,
- isPPC64 ? MVT::i64 : MVT::i32);
+ AddPromotedToType(ISD::FP_TO_UINT, MVT::i1, RegVT);
} else {
setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i1, Custom);
setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i1, Custom);
@@ -482,9 +475,8 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setOperationAction(ISD::BSWAP, MVT::i64, Legal);
} else {
setOperationAction(ISD::BSWAP, MVT::i32, Expand);
- setOperationAction(
- ISD::BSWAP, MVT::i64,
- (Subtarget.hasP9Vector() && Subtarget.isPPC64()) ? Custom : Expand);
+ setOperationAction(ISD::BSWAP, MVT::i64,
+ (Subtarget.hasP9Vector() && isPPC64) ? Custom : Expand);
}
// CTPOP or CTTZ were introduced in P8/P9 respectively
@@ -709,7 +701,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
- if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) {
+ if (Subtarget.hasLFIWAX() || isPPC64) {
setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom);
}
@@ -3191,12 +3183,11 @@ static void setUsesTOCBasePtr(SelectionDAG &DAG) {
SDValue PPCTargetLowering::getTOCEntry(SelectionDAG &DAG, const SDLoc &dl,
SDValue GA) const {
- const bool Is64Bit = Subtarget.isPPC64();
- EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
- SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT)
- : Subtarget.isAIXABI()
- ? DAG.getRegister(PPC::R2, VT)
- : DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
+ EVT VT = Subtarget.getScalarIntVT();
+ SDValue Reg = Subtarget.isPPC64() ? DAG.getRegister(PPC::X2, VT)
+ : Subtarget.isAIXABI()
+ ? DAG.getRegister(PPC::R2, VT)
+ : DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
SDValue Ops[] = { GA, Reg };
return DAG.getMemIntrinsicNode(
PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
@@ -4008,8 +3999,8 @@ SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
Entry.Node = Trmp; Args.push_back(Entry);
// TrampSize == (isPPC64 ? 48 : 40);
- Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
- isPPC64 ? MVT::i64 : MVT::i32);
+ Entry.Node =
+ DAG.getConstant(isPPC64 ? 48 : 40, dl, Subtarget.getScalarIntVT());
Args.push_back(Entry);
Entry.Node = FPtr; Args.push_back(Entry);
@@ -5237,12 +5228,11 @@ static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue Chain,
MachineFunction &MF = DAG.getMachineFunction();
const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
const PPCFrameLowering *FL = Subtarget.getFrameLowering();
- bool isPPC64 = Subtarget.isPPC64();
- int SlotSize = isPPC64 ? 8 : 4;
+ int SlotSize = Subtarget.isPPC64() ? 8 : 4;
int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
int NewRetAddr = MF.getFrameInfo().CreateFixedObject(SlotSize,
NewRetAddrLoc, true);
- EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
+ EVT VT = Subtarget.getScalarIntVT();
SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
MachinePointerInfo::getFixedStack(MF, NewRetAddr));
@@ -5253,13 +5243,13 @@ static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue Chain,
/// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
/// the position of the argument.
static void
-CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
+CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool IsPPC64,
SDValue Arg, int SPDiff, unsigned ArgOffset,
- SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
+ SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
int Offset = ArgOffset + SPDiff;
uint32_t OpSize = (Arg.getValueSizeInBits() + 7) / 8;
int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
- EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
+ EVT VT = IsPPC64 ? MVT::i64 : MVT::i32;
SDValue FIN = DAG.getFrameIndex(FI, VT);
TailCallArgumentInfo Info;
Info.Arg = Arg;
@@ -5276,7 +5266,7 @@ SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(
SDValue &FPOpOut, const SDLoc &dl) const {
if (SPDiff) {
// Load the LR and FP stack slot for later adjusting.
- EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
+ EVT VT = Subtarget.getScalarIntVT();
LROpOut = getReturnAddrFrameIndex(DAG);
LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo());
Chain = SDValue(LROpOut.getNode(), 1);
@@ -5672,7 +5662,7 @@ static void prepareDescriptorIndirectCall(SelectionDAG &DAG, SDValue &Callee,
const unsigned TOCAnchorOffset = Subtarget.descriptorTOCAnchorOffset();
const unsigned EnvPtrOffset = Subtarget.descriptorEnvironmentPointerOffset();
- const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
+ const MVT RegVT = Subtarget.getScalarIntVT();
const Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4);
// One load for the functions entry point address.
@@ -5722,9 +5712,9 @@ buildCallOperands(SmallVectorImpl<SDValue> &Ops,
SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
SDValue Glue, SDValue Chain, SDValue &Callee, int SPDiff,
const PPCSubtarget &Subtarget) {
- const bool IsPPC64 = Subtarget.isPPC64();
// MVT for a general purpose register.
- const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
+ const bool IsPPC64 = Subtarget.isPPC64();
+ const MVT RegVT = Subtarget.getScalarIntVT();
// First operand is always the chain.
Ops.push_back(Chain);
@@ -6867,7 +6857,7 @@ static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
const unsigned PtrSize = IsPPC64 ? 8 : 4;
const Align PtrAlign(PtrSize);
const Align StackAlign(16);
- const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
+ const MVT RegVT = Subtarget.getScalarIntVT();
if (ValVT == MVT::f128)
report_fatal_error("f128 is unimplemented on AIX.");
@@ -7818,7 +7808,7 @@ SDValue PPCTargetLowering::LowerCall_AIX(
assert(!CFlags.IsTailCall && "Indirect tail-calls not supported.");
const MCRegister TOCBaseReg = Subtarget.getTOCPointerRegister();
const MCRegister StackPtrReg = Subtarget.getStackPointerRegister();
- const MVT PtrVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
+ const MVT PtrVT = Subtarget.getScalarIntVT();
const unsigned TOCSaveOffset =
Subtarget.getFrameLowering()->getTOCSaveOffset();
@@ -8383,7 +8373,7 @@ static SDValue convertFPToInt(SDValue Op, SelectionDAG &DAG,
Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
}
if ((DestTy == MVT::i8 || DestTy == MVT::i16) && Subtarget.hasP9Vector())
- DestTy = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
+ DestTy = Subtarget.getScalarIntVT();
unsigned Opc = ISD::DELETED_NODE;
switch (DestTy.SimpleTy) {
default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
@@ -11319,7 +11309,7 @@ SDValue PPCTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
Val = DAG.getNode(ISD::TRUNCATE, DL, MVT::i64, Val);
}
unsigned Opcode = Subtarget.isPPC64() ? PPC::CFENCE8 : PPC::CFENCE;
- EVT FTy = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
+ EVT FTy = Subtarget.getScalarIntVT();
return SDValue(
DAG.getMachineNode(Opcode, DL, MVT::Other,
DAG.getNode(ISD::ANY_EXTEND, DL, FTy, Val),
@@ -17319,7 +17309,6 @@ SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
// the stack.
PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
FuncInfo->setLRStoreRequired();
- bool isPPC64 = Subtarget.isPPC64();
auto PtrVT = getPointerTy(MF.getDataLayout());
if (Depth > 0) {
@@ -17331,7 +17320,7 @@ SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
LowerFRAMEADDR(Op, DAG), MachinePointerInfo());
SDValue Offset =
DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(), dl,
- isPPC64 ? MVT::i64 : MVT::i32);
+ Subtarget.getScalarIntVT());
return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
MachinePointerInfo());
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h
index 2079dc0acc3cf7..f6b2722a601b6e 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -191,7 +191,7 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
}
unsigned getRedZoneSize() const {
- if (isPPC64())
+ if (IsPPC64)
// 288 bytes = 18*8 (FPRs) + 18*8 (GPRs, GPR13 reserved)
return 288;
@@ -216,8 +216,8 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
bool isSVR4ABI() const { return !isAIXABI(); }
bool isELFv2ABI() const;
- bool is64BitELFABI() const { return isSVR4ABI() && isPPC64(); }
- bool is32BitELFABI() const { return isSVR4ABI() && !isPPC64(); }
+ bool is64BitELFABI() const { return isSVR4ABI() && IsPPC64; }
+ bool is32BitELFABI() const { return isSVR4ABI() && !IsPPC64; }
bool isUsingPCRelativeCalls() const;
/// Originally, this function return hasISEL(). Now we always enable it,
@@ -246,6 +246,8 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
/// True if the GV will be accessed via an indirect symbol.
bool isGVIndirectSymbol(const GlobalValue *GV) const;
+ MVT getScalarIntVT() const { return IsPPC64 ? MVT::i64 : MVT::i32; }
+
/// Calculates the effective code model for argument GV.
CodeModel::Model getCodeModel(const TargetMachine &TM,
const GlobalValue *GV) const;
``````````
</details>
https://github.com/llvm/llvm-project/pull/115203
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