[llvm] [AArch64] Define high bits of FPR and GPR registers (take 2) (PR #114827)

[Rin Dobrescu via llvm-commits]

Rin18 wrote:

> @Rin18 would you be happy to have a look at the `V1-clear-upper-regs.s` test to see if there's any issues with the generated output? I'm not sure if there is a hidden bug in there (it seems to iterate through all subregs, including artificial ones, which may affect the output)

I took a look and compared the MCA output with and without your patch. The first thing that jumped to my attention is that your patch adds dependencies on super registers. If you run the V1-clear-upper-regs.s test with `-debug` and look at the output for the GPR32-bit test, you'll see a lot of these lines:
```
[PRF] Found a dependent use of Register X0 (defined by instruction #
```
Similarly for the other super registers in the remaining tests in that file. 

I've not been able to find the exact cause. I think this has something to do with the addition of `*_HI` registers and the fact that super registers are now described as `*sub + *sub_hi`. 



https://github.com/llvm/llvm-project/pull/114827