[llvm] [RISCV] Add +unaligned-scalar-mem to spacemit-x60 (PR #115125)

[Luke Lau via llvm-commits]

https://github.com/lukel97 created https://github.com/llvm/llvm-project/pull/115125

I can't find any official documentation on this, but from other discussions[^1] and my own testing the spacemit-x60 seems to support unaligned scalar loads and stores. 

They seem to be performant, and just from a quick test we get a 2.45% speedup on 500.perlbench_r on the Banana Pi F3[^2].

This would allow it to take advantage of #107548.

[^1]: https://github.com/llvm/llvm-project/issues/110454#issuecomment-2382199460
[^2]: https://lnt.lukelau.me/db_default/v4/nts/32


>From 05bced2a32749d4f1197dcb8bc005dbe8fc130bb Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Wed, 6 Nov 2024 14:19:19 +0800
Subject: [PATCH] [RISCV] Add +unaligned-scalar-mem to spacemit-x60

I can't find any official documentation on this, but from earlier discussions[^1] and my own testing the spacemit-x60 seems to support unaligned scalar loads and stores.

They seem to be performant, and just from a quick test we get a 2.45% speedup on 500.perlbench_r[^2].

[1]: https://github.com/llvm/llvm-project/issues/110454#issuecomment-2382199460
[2]: https://lnt.lukelau.me/db_default/v4/nts/32
---
 llvm/lib/Target/RISCV/RISCVProcessors.td | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 5277752a38ad9e..e52a856183678a 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -476,7 +476,8 @@ def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
                                         FeatureStdExtZicond,
                                         FeatureStdExtZvfh,
                                         FeatureStdExtZvkt,
-                                        FeatureStdExtZvl256b]),
+                                        FeatureStdExtZvl256b,
+                                        FeatureUnalignedScalarMem]),
                                        [TuneDLenFactor2,
                                         TuneOptimizedNF2SegmentLoadStore,
                                         TuneOptimizedNF3SegmentLoadStore,