[llvm] [DAG] SimplifyMultipleUseDemandedBits - bypass ADD nodes if either operand is zero (PR #112588)

[Simon Pilgrim via llvm-commits]

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@@ -797,6 +797,16 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedBits(
       return Op.getOperand(1);
     break;
   }
+  case ISD::ADD: {
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RKSimon wrote:

OR is already handled more generally - I'll see if I can get (SUB X, 0) to match in any tests

https://github.com/llvm/llvm-project/pull/112588