[llvm] [SelectionDAGBuilder][X86] Don't form FMAXNUM for f16 vectors if FMAXNUM needs to be promoted. (PR #114943)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=x86_64-none-unknown-elf -mattr=+avx512vl | FileCheck %s
+
+define half @r_2_10001(half %0) {
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arsenm wrote:

Named values 

https://github.com/llvm/llvm-project/pull/114943