[llvm] [SelectionDAGBuilder][X86] Don't form FMAXNUM for f16 vectors if FMAXNUM needs to be promoted. (PR #114943)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=x86_64-none-unknown-elf -mattr=+avx512vl | FileCheck %s
+
+define half @r_2_10001(half %0) {
+; CHECK-LABEL: r_2_10001:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vpextrw $0, %xmm0, %eax
+; CHECK-NEXT:    vmovd %eax, %xmm0
+; CHECK-NEXT:    vcvtph2ps %xmm0, %xmm0
+; CHECK-NEXT:    vucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT:    movl $64512, %ecx # imm = 0xFC00
+; CHECK-NEXT:    cmoval %eax, %ecx
+; CHECK-NEXT:    vpinsrw $0, %ecx, %xmm0, %xmm0
+; CHECK-NEXT:    retq
+entry:
+  %cmp2 = fcmp ogt half %0, 0xHFC00
+  %cond.v = select i1 %cmp2, half %0, half 0xHFC00
+  ret half %cond.v
+}
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arsenm wrote:

Test vector cases too? 

https://github.com/llvm/llvm-project/pull/114943