[llvm] [DAG] SimplifyDemandedBits - if we're just demanding a single shifted down sign bit, try to shift down the MSB directly (PR #114967)

[Simon Pilgrim via llvm-commits]

RKSimon wrote:

> > Yes at the moment its always the `(and (srl X, C), 1)` pattern AFAICT - if we're not going to try to extend this in the future then we can move it DAGCombine
> 
> I'm struggling to think of any other pattern where SRL by 31 would be better than SRL by a different constant.

Well, the SRL amount would be adjusted depending on the signbit and demandedbit counts - but I can't think of many patterns that would benefit (maybe mask generation from vector comparison results?).

https://github.com/llvm/llvm-project/pull/114967