[llvm] [AArch64] Define high bits of FPR and GPR registers (take 2) (PR #114827)

[Sander de Smalen via llvm-commits]

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@@ -20,33 +20,39 @@ class AArch64Reg<bits<16> enc, string n, list<Register> subregs = [],
 
 let Namespace = "AArch64" in {
   // SubRegIndexes for GPR registers
-  def sub_32 : SubRegIndex<32>;
-  def sube64 : SubRegIndex<64>;
-  def subo64 : SubRegIndex<64>;
-  def sube32 : SubRegIndex<32>;
-  def subo32 : SubRegIndex<32>;
+  def sub_32   : SubRegIndex<32,  0>;
+  def sub_32_hi: SubRegIndex<32, 32>;
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sdesmalen-arm wrote:

I've added a comment to describe the artificial cases. I'm not sure what you mean with an explicit marker though?

https://github.com/llvm/llvm-project/pull/114827