[llvm] [AArch64] Fix scheduling information for arithmetic and logical instructions. (PR #113542)

[Rin Dobrescu via llvm-commits]

Rin18 wrote:


> I'm just trying to understand if the instructions in this patch can really only go through M0, or if they can go through either M0/1 pipe (in addition to the single-cycle 0/1 pipes). M0 already has quite some instructions specific to it, including some predicate instructions, so it would be good to get this right to model its backend pressure a bit more accurately.
I see your point. My understanding is that since the SOG points to pipeline F for those instructions, then they can go through either M0/1 pipe. I selected M0 only to keep the model consistent with V1. I'm not sure what happens on average, whether pipeline M0 or M1 is used more often. If there is evidence to suggest which pipe is used less then I'll be happy to reflect this behaviour in this patch.


https://github.com/llvm/llvm-project/pull/113542