[llvm] [AArch64] Fix scheduling information for arithmetic and logical instructions. (PR #113542)

[Ricardo Jesus via llvm-commits]

rj-jesus wrote:

> Thanks for the comments, this patch does not reflect a SOG update, since the resources in group G are all part of F as well. The G unit I created in the patch is for the purpose of modelling the behaviour of instructions that use pipeline F, but have throughput of 3 rather than 4. The instructions in this patch still use resources that are part of pipeline F. This is not a new group that needs to be added to the SOG. Similar behaviour is represented in the V1 scheduling model with the J unit.

Thanks, I get your point and I agree, it's good to match the throughput reported in the SOG. I'm just trying to understand if the instructions in this patch can really only go through M0, or if they can go through either M0/1 pipe (in addition to the single-cycle 0/1 pipes). M0 already has quite some instructions specific to it, including some predicate instructions, so it would be good to get this right to model its backend pressure a bit more accurately.

https://github.com/llvm/llvm-project/pull/113542