[llvm] [AArch64] Fix scheduling information for arithmetic and logical instructions. (PR #113542)

[David Green via llvm-commits]

davemgreen wrote:

I believe that the throughput restrictions in these cases don't come from the pipelines that they can issue into but some other stage like rename or decode. Limiting the number of execution units they can use is one alternative, but in reality is can issue into any F pipeline. I have suggested in other reviews (with a different kind of instruction) that we get the pipeline features right and ignore getting the exact throughput correct. In reality it is difficult to hit this many flag-setting instructions that actually do something useful in a single cycle.

One way to fix it might be to add a new resource, which there are 3 of, that represents the number of flag-setting instructions per cycles. It might not be exactly correct as it will use that resource in the same stage as issue, not in the decode/rename stage. If we add too many of those the scheduler could start to get confused too, making sub-optimal decision because it is caring about the wrong thing. It might be worth a try though, so see if it can solve the issue that way.

https://github.com/llvm/llvm-project/pull/113542