[llvm] [AArch64] Fix scheduling information for arithmetic and logical instructions. (PR #113542)

[Rin Dobrescu via llvm-commits]

Rin18 wrote:

> Hi, thanks for these changes, in general this LGTM. Just a couple of questions:
> 
> 1. The SOG doesn't seem to mention a G group for integer single-cycle 0/1 and single/multicycle 0 pipes. Are there any plans to update the SOG to reflect this?
> 2. Except for the address generation instructions (ADR and ADRP), which have a throughput of 4, all instructions that use the F group seem to have a throughput of at best 3 according to the SOG. **If** there's going to be a discrepancy between the model and the SOG re the F group, would it be better to make the ADR* instructions the exception? In any case, if there's going to be a discrepancy, it would be good to have this documented in a comment, for example.
> 
> What do you think?

Thanks for the comments, this patch does not reflect a SOG update, since the resources in group G are all part of F as well.
The G unit I created in the patch is for the purpose of modelling the behaviour of instructions that use pipeline F, but have throughput of 3 rather than 4. The instructions in this patch still use resources that are part of pipeline F.  This is not a new group that needs to be added to the SOG. Similar behaviour is represented in the V1 scheduling model with the J unit. 

https://github.com/llvm/llvm-project/pull/113542