[llvm] [AArch64] Fix scheduling information for arithmetic and logical instructions. (PR #113542)

[Ricardo Jesus via llvm-commits]

https://github.com/rj-jesus commented:

Hi, thanks for these changes, in general this LGTM. Just a couple of questions:
1. The SOG doesn't seem to mention a G group for integer single-cycle 0/1 and single/multicycle 0 pipes. Are there any plans to update the SOG to reflect this?
2. Except for the address generation instructions (ADR and ADRP), which have a throughput of 4, all instructions that use the F group seem to have a throughput of at best 3 according to the SOG. **If** there's going to be a discrepancy between the model and the SOG re the F group, would it be better to make the ADR* instructions the exception? In any case, if there's going to be a discrepancy, it would be good to have this documented in a comment, for example.

What do you think?

https://github.com/llvm/llvm-project/pull/113542