[llvm] [DAG] SimplifyMultipleUseDemandedBits - bypass ADD nodes if either operand is zero (PR #112588)

[Phoebe Wang via llvm-commits]

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@@ -55,7 +55,7 @@ define i32 @mul_4xi8_zc(<4 x i8> %a, i32 %c) {
 ; AVX512VLVNNI-NEXT:    retq
 entry:
   %0 = zext <4 x i8> %a to <4 x i32>
-  %1 = mul nsw <4 x i32> %0, <i32 0, i32 1, i32 2, i32 127>
+  %1 = mul nsw <4 x i32> %0, <i32 16, i32 1, i32 2, i32 127>
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phoebewang wrote:

Why changing test case?

https://github.com/llvm/llvm-project/pull/112588