[llvm] [DAG] SimplifyMultipleUseDemandedBits - bypass ADD nodes if either operand is zero (PR #112588)

[Simon Pilgrim via llvm-commits]

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@@ -39,8 +39,8 @@ define amdgpu_kernel void @srem_i16_7(ptr addrspace(1) %out, ptr addrspace(1) %i
 ; TAHITI-NEXT:    s_waitcnt vmcnt(0)
 ; TAHITI-NEXT:    v_readfirstlane_b32 s0, v0
 ; TAHITI-NEXT:    s_mulk_i32 s0, 0x4925
-; TAHITI-NEXT:    s_lshr_b32 s1, s0, 31
 ; TAHITI-NEXT:    s_ashr_i32 s0, s0, 17
+; TAHITI-NEXT:    s_bfe_u32 s1, s0, 0x1000f
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RKSimon wrote:

@arsenm @jayfoad Have we missed a fold here? Is BFE better than SRL?

https://github.com/llvm/llvm-project/pull/112588