[llvm] [RISCV] Use RVInst16CB for C_SRLI64_HINT and C_SRAI64_HINT. (PR #112250)

[Sam Elliott via llvm-commits]

lenary wrote:

I'm not talking about the CompressPat, I'm talking about once you have a `C_ANDI`, and you ask for its encoding using `getBinaryCodeForInstr`, that calls `getMachineOpValue` for the `rd` operand (the RVC-encoded register). `getMachineOpValue` returns the 5-bit encoding, which then the generated code in `getBinaryCodeForInstr` masks down to 3 bits to put the right bits in the instruction encoding. In that code there is no assert that we actually have an RVC register, rather than another register, though maybe that's not the right place in the backend to check that - I don't know where that code would be.

But I find it interesting that we don't have something like a tablegen instance of `RegisterOperand` with a custom `EncoderMethod`, and instead just trust the extraction of 3 bits from the 5 provided by `getMachineOpValue`.

To be clear, I've not found a bug, I just have an instinct not to trust this kind of implicit behaviour.

https://github.com/llvm/llvm-project/pull/112250